1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright 2021-2026 NXP 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller 9 10maintainers: 11 - Jan Petrous (OSS) <jan.petrous@oss.nxp.com> 12 13description: 14 This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs. 15 The SoC series S32G2xx and S32G3xx feature one DWMAC instance, 16 the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII 17 interface over Pinctrl device or the output can be routed 18 to the embedded SerDes for SGMII connectivity. 19 The DWMAC instances have connected all RX/TX queues interrupts, 20 enabling load balancing of data traffic across all CPU cores. 21 22properties: 23 compatible: 24 oneOf: 25 - const: nxp,s32g2-dwmac 26 - items: 27 - enum: 28 - nxp,s32g3-dwmac 29 - nxp,s32r45-dwmac 30 - const: nxp,s32g2-dwmac 31 32 reg: 33 items: 34 - description: Main GMAC registers 35 - description: GMAC PHY mode control register 36 37 nxp,phy-sel: 38 $ref: /schemas/types.yaml#/definitions/phandle-array 39 items: 40 - items: 41 - description: phandle to the GPR syscon node 42 - description: offset of PHY selection register 43 description: 44 This phandle points to the GMAC_0_CTRL_STS register which controls the 45 GMAC_0 configuration options. The register lets you select the PHY 46 interface and the PHY mode. It also controls if the FTM_0 or FTM_1 47 FlexTimer Modules connect to GMAC_0. 48 49 interrupts: 50 minItems: 1 51 maxItems: 11 52 53 interrupt-names: 54 oneOf: 55 - items: 56 - const: macirq 57 - items: 58 - const: macirq 59 - const: tx-queue-0 60 - const: rx-queue-0 61 - const: tx-queue-1 62 - const: rx-queue-1 63 - const: tx-queue-2 64 - const: rx-queue-2 65 - const: tx-queue-3 66 - const: rx-queue-3 67 - const: tx-queue-4 68 - const: rx-queue-4 69 70 clocks: 71 items: 72 - description: Main GMAC clock 73 - description: Transmit clock 74 - description: Receive clock 75 - description: PTP reference clock 76 77 clock-names: 78 items: 79 - const: stmmaceth 80 - const: tx 81 - const: rx 82 - const: ptp_ref 83 84required: 85 - clocks 86 - clock-names 87 88allOf: 89 - $ref: snps,dwmac.yaml# 90 91unevaluatedProperties: false 92 93examples: 94 - | 95 #include <dt-bindings/interrupt-controller/arm-gic.h> 96 #include <dt-bindings/interrupt-controller/irq.h> 97 #include <dt-bindings/phy/phy.h> 98 bus { 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ethernet@4033c000 { 103 compatible = "nxp,s32g2-dwmac"; 104 reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ 105 <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ 106 nxp,phy-sel = <&gpr 0x4>; 107 interrupt-parent = <&gic>; 108 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 109 /* CHN 0: tx, rx */ 110 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 112 /* CHN 1: tx, rx */ 113 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 115 /* CHN 2: tx, rx */ 116 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 118 /* CHN 3: tx, rx */ 119 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 121 /* CHN 4: tx, rx */ 122 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 124 interrupt-names = "macirq", 125 "tx-queue-0", "rx-queue-0", 126 "tx-queue-1", "rx-queue-1", 127 "tx-queue-2", "rx-queue-2", 128 "tx-queue-3", "rx-queue-3", 129 "tx-queue-4", "rx-queue-4"; 130 snps,mtl-rx-config = <&mtl_rx_setup>; 131 snps,mtl-tx-config = <&mtl_tx_setup>; 132 clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; 133 clock-names = "stmmaceth", "tx", "rx", "ptp_ref"; 134 phy-mode = "rgmii-id"; 135 phy-handle = <&phy0>; 136 137 mtl_rx_setup: rx-queues-config { 138 snps,rx-queues-to-use = <5>; 139 }; 140 141 mtl_tx_setup: tx-queues-config { 142 snps,tx-queues-to-use = <5>; 143 }; 144 145 mdio { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "snps,dwmac-mdio"; 149 150 phy0: ethernet-phy@0 { 151 reg = <0>; 152 }; 153 }; 154 }; 155 }; 156