xref: /linux/Documentation/devicetree/bindings/net/mscc,miim.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mscc,miim.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microsemi MII Management Controller (MIIM)
8
9maintainers:
10  - Alexandre Belloni <alexandre.belloni@bootlin.com>
11
12allOf:
13  - $ref: mdio.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - enum:
19          - mscc,ocelot-miim
20          - microchip,lan966x-miim
21      - items:
22          - enum:
23              - microchip,lan9691-miim
24          - const: mscc,ocelot-miim
25
26  "#address-cells":
27    const: 1
28
29  "#size-cells":
30    const: 0
31
32  reg:
33    items:
34      - description: base address
35      - description: associated reset register for internal PHYs
36    minItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  clocks:
42    maxItems: 1
43
44  clock-frequency: true
45
46  resets:
47    items:
48      - description:
49          Reset shared with all blocks attached to the Switch Core Register
50          Bus (CSR) including VRAP slave.
51
52  reset-names:
53    items:
54      - const: switch
55
56required:
57  - compatible
58  - reg
59  - "#address-cells"
60  - "#size-cells"
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    mdio@107009c {
67      compatible = "mscc,ocelot-miim";
68      reg = <0x107009c 0x36>, <0x10700f0 0x8>;
69      interrupts = <14>;
70      #address-cells = <1>;
71      #size-cells = <0>;
72
73      phy0: ethernet-phy@0 {
74        reg = <0>;
75      };
76    };
77