1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip Sparx5 Ethernet switch controller 8 9maintainers: 10 - Steen Hegelund <steen.hegelund@microchip.com> 11 - Lars Povlsen <lars.povlsen@microchip.com> 12 13description: | 14 The SparX-5 Enterprise Ethernet switch family provides a rich set of 15 Enterprise switching features such as advanced TCAM-based VLAN and 16 QoS processing enabling delivery of differentiated services, and 17 security through TCAM-based frame processing using versatile content 18 aware processor (VCAP). 19 20 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported 21 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K 22 IPv6 (S,G) multicast groups. 23 24 L3 security features include source guard and reverse path 25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and 26 IP tunnels (IP over GRE/IP). 27 28 The SparX-5 switch family targets managed Layer 2 and Layer 3 29 equipment in SMB, SME, and Enterprise where high port count 30 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required. 31 32properties: 33 $nodename: 34 pattern: "^switch@[0-9a-f]+$" 35 36 compatible: 37 const: microchip,sparx5-switch 38 39 reg: 40 items: 41 - description: cpu target 42 - description: devices target 43 - description: general control block target 44 45 reg-names: 46 items: 47 - const: cpu 48 - const: devices 49 - const: gcb 50 51 interrupts: 52 minItems: 1 53 items: 54 - description: register based extraction 55 - description: frame dma based extraction 56 57 interrupt-names: 58 minItems: 1 59 items: 60 - const: xtr 61 - const: fdma 62 63 resets: 64 items: 65 - description: Reset controller used for switch core reset (soft reset) 66 67 reset-names: 68 items: 69 - const: switch 70 71 mac-address: true 72 73 ethernet-ports: 74 type: object 75 patternProperties: 76 "^port@[0-9a-f]+$": 77 type: object 78 79 properties: 80 '#address-cells': 81 const: 1 82 '#size-cells': 83 const: 0 84 85 reg: 86 description: Switch port number 87 88 phys: 89 maxItems: 1 90 description: 91 phandle of a Ethernet SerDes PHY. This defines which SerDes 92 instance will handle the Ethernet traffic. 93 94 phy-mode: 95 description: 96 This specifies the interface used by the Ethernet SerDes towards 97 the PHY or SFP. 98 99 microchip,bandwidth: 100 description: Specifies bandwidth in Mbit/s allocated to the port. 101 $ref: "/schemas/types.yaml#/definitions/uint32" 102 maximum: 25000 103 104 phy-handle: 105 description: 106 phandle of a Ethernet PHY. This is optional and if provided it 107 points to the cuPHY used by the Ethernet SerDes. 108 109 sfp: 110 description: 111 phandle of an SFP. This is optional and used when not specifying 112 a cuPHY. It points to the SFP node that describes the SFP used by 113 the Ethernet SerDes. 114 115 managed: true 116 117 microchip,sd-sgpio: 118 description: 119 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs 120 This is optional, and only needed if the default used index is 121 is not correct. 122 $ref: "/schemas/types.yaml#/definitions/uint32" 123 minimum: 0 124 maximum: 383 125 126 required: 127 - reg 128 - phys 129 - phy-mode 130 - microchip,bandwidth 131 132 oneOf: 133 - required: 134 - phy-handle 135 - required: 136 - sfp 137 - managed 138 139required: 140 - compatible 141 - reg 142 - reg-names 143 - interrupts 144 - interrupt-names 145 - resets 146 - reset-names 147 - ethernet-ports 148 149additionalProperties: false 150 151examples: 152 - | 153 #include <dt-bindings/interrupt-controller/arm-gic.h> 154 switch: switch@600000000 { 155 compatible = "microchip,sparx5-switch"; 156 reg = <0 0x401000>, 157 <0x10004000 0x7fc000>, 158 <0x11010000 0xaf0000>; 159 reg-names = "cpu", "devices", "gcb"; 160 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 161 interrupt-names = "xtr"; 162 resets = <&reset 0>; 163 reset-names = "switch"; 164 ethernet-ports { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 port0: port@0 { 169 reg = <0>; 170 microchip,bandwidth = <1000>; 171 phys = <&serdes 13>; 172 phy-handle = <&phy0>; 173 phy-mode = "qsgmii"; 174 }; 175 /* ... */ 176 /* Then the 25G interfaces */ 177 port60: port@60 { 178 reg = <60>; 179 microchip,bandwidth = <25000>; 180 phys = <&serdes 29>; 181 phy-mode = "10gbase-r"; 182 sfp = <&sfp_eth60>; 183 managed = "in-band-status"; 184 microchip,sd-sgpio = <365>; 185 }; 186 port61: port@61 { 187 reg = <61>; 188 microchip,bandwidth = <25000>; 189 phys = <&serdes 30>; 190 phy-mode = "10gbase-r"; 191 sfp = <&sfp_eth61>; 192 managed = "in-band-status"; 193 microchip,sd-sgpio = <369>; 194 }; 195 port62: port@62 { 196 reg = <62>; 197 microchip,bandwidth = <25000>; 198 phys = <&serdes 31>; 199 phy-mode = "10gbase-r"; 200 sfp = <&sfp_eth62>; 201 managed = "in-band-status"; 202 microchip,sd-sgpio = <373>; 203 }; 204 port63: port@63 { 205 reg = <63>; 206 microchip,bandwidth = <25000>; 207 phys = <&serdes 32>; 208 phy-mode = "10gbase-r"; 209 sfp = <&sfp_eth63>; 210 managed = "in-band-status"; 211 microchip,sd-sgpio = <377>; 212 }; 213 /* Finally the Management interface */ 214 port64: port@64 { 215 reg = <64>; 216 microchip,bandwidth = <1000>; 217 phys = <&serdes 0>; 218 phy-handle = <&phy64>; 219 phy-mode = "sgmii"; 220 mac-address = [ 00 00 00 01 02 03 ]; 221 }; 222 }; 223 }; 224 225... 226# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml : 227