1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip Sparx5 Ethernet switch controller 8 9maintainers: 10 - Steen Hegelund <steen.hegelund@microchip.com> 11 - Lars Povlsen <lars.povlsen@microchip.com> 12 - Daniel Machon <daniel.machon@microchip.com> 13 14description: | 15 The SparX-5 Enterprise Ethernet switch family provides a rich set of 16 Enterprise switching features such as advanced TCAM-based VLAN and 17 QoS processing enabling delivery of differentiated services, and 18 security through TCAM-based frame processing using versatile content 19 aware processor (VCAP). 20 21 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported 22 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K 23 IPv6 (S,G) multicast groups. 24 25 L3 security features include source guard and reverse path 26 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and 27 IP tunnels (IP over GRE/IP). 28 29 The SparX-5 switch family targets managed Layer 2 and Layer 3 30 equipment in SMB, SME, and Enterprise where high port count 31 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required. 32 33properties: 34 $nodename: 35 pattern: "^switch@[0-9a-f]+$" 36 37 compatible: 38 oneOf: 39 - enum: 40 - microchip,lan9691-switch 41 - microchip,sparx5-switch 42 - items: 43 - enum: 44 - microchip,lan969c-switch 45 - microchip,lan969b-switch 46 - microchip,lan969a-switch 47 - microchip,lan9699-switch 48 - microchip,lan9698-switch 49 - microchip,lan9697-switch 50 - microchip,lan9696-switch 51 - microchip,lan9695-switch 52 - microchip,lan9694-switch 53 - microchip,lan9693-switch 54 - microchip,lan9692-switch 55 - const: microchip,lan9691-switch 56 57 reg: 58 items: 59 - description: cpu target 60 - description: devices target 61 - description: general control block target 62 63 reg-names: 64 items: 65 - const: cpu 66 - const: devices 67 - const: gcb 68 69 interrupts: 70 minItems: 1 71 items: 72 - description: register based extraction 73 - description: frame dma based extraction 74 - description: ptp interrupt 75 76 interrupt-names: 77 minItems: 1 78 items: 79 - const: xtr 80 - const: fdma 81 - const: ptp 82 83 resets: 84 items: 85 - description: Reset controller used for switch core reset (soft reset) 86 87 reset-names: 88 items: 89 - const: switch 90 91 mac-address: true 92 93 ethernet-ports: 94 type: object 95 additionalProperties: false 96 97 properties: 98 '#address-cells': 99 const: 1 100 '#size-cells': 101 const: 0 102 103 patternProperties: 104 "^port@[0-9a-f]+$": 105 $ref: /schemas/net/ethernet-controller.yaml# 106 unevaluatedProperties: false 107 108 properties: 109 reg: 110 description: Switch port number 111 112 phys: 113 maxItems: 1 114 description: 115 phandle of a Ethernet SerDes PHY. This defines which SerDes 116 instance will handle the Ethernet traffic. 117 118 microchip,bandwidth: 119 description: Specifies bandwidth in Mbit/s allocated to the port. 120 $ref: /schemas/types.yaml#/definitions/uint32 121 maximum: 25000 122 123 microchip,sd-sgpio: 124 description: 125 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs 126 This is optional, and only needed if the default used index is 127 is not correct. 128 $ref: /schemas/types.yaml#/definitions/uint32 129 minimum: 0 130 maximum: 383 131 132 required: 133 - reg 134 - phys 135 - phy-mode 136 - microchip,bandwidth 137 138 oneOf: 139 - required: 140 - phy-handle 141 - required: 142 - sfp 143 - managed 144 145required: 146 - compatible 147 - reg 148 - reg-names 149 - interrupts 150 - interrupt-names 151 - ethernet-ports 152 153additionalProperties: false 154 155examples: 156 - | 157 #include <dt-bindings/interrupt-controller/arm-gic.h> 158 switch: switch@600000000 { 159 compatible = "microchip,sparx5-switch"; 160 reg = <0 0x401000>, 161 <0x10004000 0x7fc000>, 162 <0x11010000 0xaf0000>; 163 reg-names = "cpu", "devices", "gcb"; 164 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 165 interrupt-names = "xtr"; 166 resets = <&reset 0>; 167 reset-names = "switch"; 168 ethernet-ports { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 port0: port@0 { 173 reg = <0>; 174 microchip,bandwidth = <1000>; 175 phys = <&serdes 13>; 176 phy-handle = <&phy0>; 177 phy-mode = "qsgmii"; 178 }; 179 /* ... */ 180 /* Then the 25G interfaces */ 181 port60: port@60 { 182 reg = <60>; 183 microchip,bandwidth = <25000>; 184 phys = <&serdes 29>; 185 phy-mode = "10gbase-r"; 186 sfp = <&sfp_eth60>; 187 managed = "in-band-status"; 188 microchip,sd-sgpio = <365>; 189 }; 190 port61: port@61 { 191 reg = <61>; 192 microchip,bandwidth = <25000>; 193 phys = <&serdes 30>; 194 phy-mode = "10gbase-r"; 195 sfp = <&sfp_eth61>; 196 managed = "in-band-status"; 197 microchip,sd-sgpio = <369>; 198 }; 199 port62: port@62 { 200 reg = <62>; 201 microchip,bandwidth = <25000>; 202 phys = <&serdes 31>; 203 phy-mode = "10gbase-r"; 204 sfp = <&sfp_eth62>; 205 managed = "in-band-status"; 206 microchip,sd-sgpio = <373>; 207 }; 208 port63: port@63 { 209 reg = <63>; 210 microchip,bandwidth = <25000>; 211 phys = <&serdes 32>; 212 phy-mode = "10gbase-r"; 213 sfp = <&sfp_eth63>; 214 managed = "in-band-status"; 215 microchip,sd-sgpio = <377>; 216 }; 217 /* Finally the Management interface */ 218 port64: port@64 { 219 reg = <64>; 220 microchip,bandwidth = <1000>; 221 phys = <&serdes 0>; 222 phy-handle = <&phy64>; 223 phy-mode = "sgmii"; 224 mac-address = [ 00 00 00 01 02 03 ]; 225 }; 226 }; 227 }; 228 229... 230# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml : 231