xref: /linux/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml (revision 45bd2d77fbedec862204bb5c0fcaba2b7fa5fb56) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/microchip,pic64hpsc-mdio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PIC64-HPSC/HX MDIO controller
8
9maintainers:
10  - Charles Perry <charles.perry@microchip.com>
11
12description:
13  This is the MDIO bus controller present in Microchip PIC64-HPSC/HX SoCs. It
14  supports C22 and C45 register access and is named "MDIO Initiator" in the
15  documentation.
16
17allOf:
18  - $ref: mdio.yaml#
19
20properties:
21  compatible:
22    oneOf:
23      - const: microchip,pic64hpsc-mdio
24      - items:
25          - const: microchip,pic64hx-mdio
26          - const: microchip,pic64hpsc-mdio
27
28  reg:
29    maxItems: 1
30
31  clocks:
32    maxItems: 1
33
34  clock-frequency:
35    default: 2500000
36
37  interrupts:
38    maxItems: 1
39
40required:
41  - compatible
42  - reg
43  - clocks
44  - interrupts
45
46unevaluatedProperties: false
47
48examples:
49  - |
50    #include <dt-bindings/interrupt-controller/irq.h>
51    bus {
52        #address-cells = <2>;
53        #size-cells = <2>;
54
55        mdio@4000c21e000 {
56            compatible = "microchip,pic64hpsc-mdio";
57            reg = <0x400 0x0c21e000 0x0 0x1000>;
58            #address-cells = <1>;
59            #size-cells = <0>;
60            clocks = <&svc_clk>;
61            interrupt-parent = <&saplic0>;
62            interrupts = <168 IRQ_TYPE_LEVEL_HIGH>;
63
64            ethernet-phy@0 {
65                reg = <0>;
66            };
67        };
68    };
69