xref: /linux/Documentation/devicetree/bindings/net/micrel,gigabit.yaml (revision 283d58723887091eff3fd4ecc8eaa9d480d0a40e)
1*283d5872SStefan Eichenberger# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*283d5872SStefan Eichenberger%YAML 1.2
3*283d5872SStefan Eichenberger---
4*283d5872SStefan Eichenberger$id: http://devicetree.org/schemas/net/micrel,gigabit.yaml#
5*283d5872SStefan Eichenberger$schema: http://devicetree.org/meta-schemas/core.yaml#
6*283d5872SStefan Eichenberger
7*283d5872SStefan Eichenbergertitle: Micrel series Gigabit Ethernet PHYs
8*283d5872SStefan Eichenberger
9*283d5872SStefan Eichenbergermaintainers:
10*283d5872SStefan Eichenberger  - Andrew Lunn <andrew@lunn.ch>
11*283d5872SStefan Eichenberger  - Stefan Eichenberger <eichest@gmail.com>
12*283d5872SStefan Eichenberger
13*283d5872SStefan Eichenbergerdescription:
14*283d5872SStefan Eichenberger  Some boards require special skew tuning values, particularly when it comes
15*283d5872SStefan Eichenberger  to clock delays. These values can be specified in the device tree using
16*283d5872SStefan Eichenberger  the properties listed here.
17*283d5872SStefan Eichenberger
18*283d5872SStefan Eichenbergerproperties:
19*283d5872SStefan Eichenberger  compatible:
20*283d5872SStefan Eichenberger    enum:
21*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1610  # KSZ9021
22*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1611  # KSZ9021RLRN
23*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1620  # KSZ9031
24*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1631  # KSZ9477
25*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1640  # KSZ9131
26*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1650  # LAN8841
27*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1660  # LAN8814
28*283d5872SStefan Eichenberger      - ethernet-phy-id0022.1670  # LAN8804
29*283d5872SStefan Eichenberger
30*283d5872SStefan Eichenberger  micrel,force-master:
31*283d5872SStefan Eichenberger    type: boolean
32*283d5872SStefan Eichenberger    description: |
33*283d5872SStefan Eichenberger      Force phy to master mode. Only set this option if the phy reference
34*283d5872SStefan Eichenberger      clock provided at CLK125_NDO pin is used as MAC reference clock
35*283d5872SStefan Eichenberger      because the clock jitter in slave mode is too high (errata#2).
36*283d5872SStefan Eichenberger      Attention: The link partner must be configurable as slave otherwise
37*283d5872SStefan Eichenberger      no link will be established.
38*283d5872SStefan Eichenberger
39*283d5872SStefan Eichenberger  coma-mode-gpios:
40*283d5872SStefan Eichenberger    maxItems: 1
41*283d5872SStefan Eichenberger    description: |
42*283d5872SStefan Eichenberger      If present the given gpio will be deasserted when the PHY is probed.
43*283d5872SStefan Eichenberger
44*283d5872SStefan Eichenberger      Some PHYs have a COMA mode input pin which puts the PHY into
45*283d5872SStefan Eichenberger      isolate and power-down mode. On some boards this input is connected
46*283d5872SStefan Eichenberger      to a GPIO of the SoC.
47*283d5872SStefan Eichenberger
48*283d5872SStefan Eichenberger  micrel,led-mode:
49*283d5872SStefan Eichenberger    $ref: /schemas/types.yaml#/definitions/uint32
50*283d5872SStefan Eichenberger    description: |
51*283d5872SStefan Eichenberger      LED mode value to set for PHYs with configurable LEDs.
52*283d5872SStefan Eichenberger
53*283d5872SStefan Eichenberger      Configure the LED mode with single value. The list of PHYs and the
54*283d5872SStefan Eichenberger      bits that are currently supported:
55*283d5872SStefan Eichenberger
56*283d5872SStefan Eichenberger      LAN8814: register EP5.0, bit 6
57*283d5872SStefan Eichenberger
58*283d5872SStefan Eichenberger      See the respective PHY datasheet for the mode values.
59*283d5872SStefan Eichenberger    minimum: 0
60*283d5872SStefan Eichenberger    maximum: 1
61*283d5872SStefan Eichenberger
62*283d5872SStefan EichenbergerpatternProperties:
63*283d5872SStefan Eichenberger  '^([rt]xc)-skew-psec$':
64*283d5872SStefan Eichenberger    $ref: /schemas/types.yaml#/definitions/int32
65*283d5872SStefan Eichenberger    description:
66*283d5872SStefan Eichenberger      Skew control of the pad in picoseconds.
67*283d5872SStefan Eichenberger    minimum: -700
68*283d5872SStefan Eichenberger    maximum: 2400
69*283d5872SStefan Eichenberger    multipleOf: 100
70*283d5872SStefan Eichenberger    default: 0
71*283d5872SStefan Eichenberger
72*283d5872SStefan Eichenberger  '^([rt]xd[0-3]|rxdv|txen)-skew-psec$':
73*283d5872SStefan Eichenberger    $ref: /schemas/types.yaml#/definitions/int32
74*283d5872SStefan Eichenberger    description: |
75*283d5872SStefan Eichenberger      Skew control of the pad in picoseconds.
76*283d5872SStefan Eichenberger    minimum: -700
77*283d5872SStefan Eichenberger    maximum: 800
78*283d5872SStefan Eichenberger    multipleOf: 100
79*283d5872SStefan Eichenberger    default: 0
80*283d5872SStefan Eichenberger
81*283d5872SStefan EichenbergerallOf:
82*283d5872SStefan Eichenberger  - $ref: ethernet-phy.yaml#
83*283d5872SStefan Eichenberger  - if:
84*283d5872SStefan Eichenberger      properties:
85*283d5872SStefan Eichenberger        compatible:
86*283d5872SStefan Eichenberger          contains:
87*283d5872SStefan Eichenberger            enum:
88*283d5872SStefan Eichenberger              - ethernet-phy-id0022.1610
89*283d5872SStefan Eichenberger              - ethernet-phy-id0022.1611
90*283d5872SStefan Eichenberger    then:
91*283d5872SStefan Eichenberger      patternProperties:
92*283d5872SStefan Eichenberger        '^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-ps$':
93*283d5872SStefan Eichenberger          description: |
94*283d5872SStefan Eichenberger            Skew control of the pad in picoseconds.
95*283d5872SStefan Eichenberger            The actual increment on the chip is 120ps ranging from -840ps to
96*283d5872SStefan Eichenberger            960ps, this mismatch comes from a documentation error before
97*283d5872SStefan Eichenberger            datasheet revision 1.2 (Feb 2014).
98*283d5872SStefan Eichenberger
99*283d5872SStefan Eichenberger            The device tree value to delay mapping looks as follows:
100*283d5872SStefan Eichenberger            Device Tree Value   Delay
101*283d5872SStefan Eichenberger            --------------------------
102*283d5872SStefan Eichenberger            0                   -840ps
103*283d5872SStefan Eichenberger            200                 -720ps
104*283d5872SStefan Eichenberger            400                 -600ps
105*283d5872SStefan Eichenberger            600                 -480ps
106*283d5872SStefan Eichenberger            800                 -360ps
107*283d5872SStefan Eichenberger            1000                -240ps
108*283d5872SStefan Eichenberger            1200                -120ps
109*283d5872SStefan Eichenberger            1400                   0ps
110*283d5872SStefan Eichenberger            1600                 120ps
111*283d5872SStefan Eichenberger            1800                 240ps
112*283d5872SStefan Eichenberger            2000                 360ps
113*283d5872SStefan Eichenberger            2200                 480ps
114*283d5872SStefan Eichenberger            2400                 600ps
115*283d5872SStefan Eichenberger            2600                 720ps
116*283d5872SStefan Eichenberger            2800                 840ps
117*283d5872SStefan Eichenberger            3000                 960ps
118*283d5872SStefan Eichenberger          minimum: 0
119*283d5872SStefan Eichenberger          maximum: 3000
120*283d5872SStefan Eichenberger          multipleOf: 200
121*283d5872SStefan Eichenberger          default: 1400
122*283d5872SStefan Eichenberger  - if:
123*283d5872SStefan Eichenberger      properties:
124*283d5872SStefan Eichenberger        compatible:
125*283d5872SStefan Eichenberger          contains:
126*283d5872SStefan Eichenberger            const: ethernet-phy-id0022.1620
127*283d5872SStefan Eichenberger    then:
128*283d5872SStefan Eichenberger      patternProperties:
129*283d5872SStefan Eichenberger        '^([rt]xc)-skew-ps$':
130*283d5872SStefan Eichenberger          description: |
131*283d5872SStefan Eichenberger            Skew control of the pad in picoseconds.
132*283d5872SStefan Eichenberger
133*283d5872SStefan Eichenberger            The device tree value to delay mapping is as follows:
134*283d5872SStefan Eichenberger            Device Tree Value   Delay
135*283d5872SStefan Eichenberger            --------------------------
136*283d5872SStefan Eichenberger            0                   -900ps
137*283d5872SStefan Eichenberger            60                  -840ps
138*283d5872SStefan Eichenberger            120                 -780ps
139*283d5872SStefan Eichenberger            180                 -720ps
140*283d5872SStefan Eichenberger            240                 -660ps
141*283d5872SStefan Eichenberger            300                 -600ps
142*283d5872SStefan Eichenberger            360                 -540ps
143*283d5872SStefan Eichenberger            420                 -480ps
144*283d5872SStefan Eichenberger            480                 -420ps
145*283d5872SStefan Eichenberger            540                 -360ps
146*283d5872SStefan Eichenberger            600                 -300ps
147*283d5872SStefan Eichenberger            660                 -240ps
148*283d5872SStefan Eichenberger            720                 -180ps
149*283d5872SStefan Eichenberger            780                 -120ps
150*283d5872SStefan Eichenberger            840                  -60ps
151*283d5872SStefan Eichenberger            900                    0ps
152*283d5872SStefan Eichenberger            960                   60ps
153*283d5872SStefan Eichenberger            1020                 120ps
154*283d5872SStefan Eichenberger            1080                 180ps
155*283d5872SStefan Eichenberger            1140                 240ps
156*283d5872SStefan Eichenberger            1200                 300ps
157*283d5872SStefan Eichenberger            1260                 360ps
158*283d5872SStefan Eichenberger            1320                 420ps
159*283d5872SStefan Eichenberger            1380                 480ps
160*283d5872SStefan Eichenberger            1440                 540ps
161*283d5872SStefan Eichenberger            1500                 600ps
162*283d5872SStefan Eichenberger            1560                 660ps
163*283d5872SStefan Eichenberger            1620                 720ps
164*283d5872SStefan Eichenberger            1680                 780ps
165*283d5872SStefan Eichenberger            1740                 840ps
166*283d5872SStefan Eichenberger            1800                 900ps
167*283d5872SStefan Eichenberger            1860                 960ps
168*283d5872SStefan Eichenberger          minimum: 0
169*283d5872SStefan Eichenberger          maximum: 1860
170*283d5872SStefan Eichenberger          multipleOf: 60
171*283d5872SStefan Eichenberger          default: 900
172*283d5872SStefan Eichenberger        '^([rt]xd[0-3]|rxdv|txen)-skew-ps$':
173*283d5872SStefan Eichenberger          description: |
174*283d5872SStefan Eichenberger            Skew control of the pad in picoseconds.
175*283d5872SStefan Eichenberger
176*283d5872SStefan Eichenberger            The device tree value to delay mapping is as follows:
177*283d5872SStefan Eichenberger            Device Tree Value   Delay
178*283d5872SStefan Eichenberger            --------------------------
179*283d5872SStefan Eichenberger            0                   -420ps
180*283d5872SStefan Eichenberger            60                  -360ps
181*283d5872SStefan Eichenberger            120                 -300ps
182*283d5872SStefan Eichenberger            180                 -240ps
183*283d5872SStefan Eichenberger            240                 -180ps
184*283d5872SStefan Eichenberger            300                 -120ps
185*283d5872SStefan Eichenberger            360                  -60ps
186*283d5872SStefan Eichenberger            420                    0ps
187*283d5872SStefan Eichenberger            480                   60ps
188*283d5872SStefan Eichenberger            540                  120ps
189*283d5872SStefan Eichenberger            600                  180ps
190*283d5872SStefan Eichenberger            660                  240ps
191*283d5872SStefan Eichenberger            720                  300ps
192*283d5872SStefan Eichenberger            780                  360ps
193*283d5872SStefan Eichenberger            840                  420ps
194*283d5872SStefan Eichenberger            900                  480ps
195*283d5872SStefan Eichenberger          minimum: 0
196*283d5872SStefan Eichenberger          maximum: 900
197*283d5872SStefan Eichenberger          multipleOf: 60
198*283d5872SStefan Eichenberger          default: 420
199*283d5872SStefan Eichenberger  - if:
200*283d5872SStefan Eichenberger      not:
201*283d5872SStefan Eichenberger        properties:
202*283d5872SStefan Eichenberger          compatible:
203*283d5872SStefan Eichenberger            contains:
204*283d5872SStefan Eichenberger              enum:
205*283d5872SStefan Eichenberger                - ethernet-phy-id0022.1640
206*283d5872SStefan Eichenberger                - ethernet-phy-id0022.1650
207*283d5872SStefan Eichenberger    then:
208*283d5872SStefan Eichenberger      patternProperties:
209*283d5872SStefan Eichenberger        '^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-psec$': false
210*283d5872SStefan Eichenberger  - if:
211*283d5872SStefan Eichenberger      not:
212*283d5872SStefan Eichenberger        properties:
213*283d5872SStefan Eichenberger          compatible:
214*283d5872SStefan Eichenberger            contains:
215*283d5872SStefan Eichenberger              const: ethernet-phy-id0022.1620
216*283d5872SStefan Eichenberger    then:
217*283d5872SStefan Eichenberger      properties:
218*283d5872SStefan Eichenberger        micrel,force-master: false
219*283d5872SStefan Eichenberger  - if:
220*283d5872SStefan Eichenberger      not:
221*283d5872SStefan Eichenberger        properties:
222*283d5872SStefan Eichenberger          compatible:
223*283d5872SStefan Eichenberger            contains:
224*283d5872SStefan Eichenberger              const: ethernet-phy-id0022.1660
225*283d5872SStefan Eichenberger    then:
226*283d5872SStefan Eichenberger      properties:
227*283d5872SStefan Eichenberger        coma-mode-gpios: false
228*283d5872SStefan Eichenberger        micrel,led-mode: false
229*283d5872SStefan Eichenberger
230*283d5872SStefan EichenbergerunevaluatedProperties: false
231*283d5872SStefan Eichenberger
232*283d5872SStefan Eichenbergerexamples:
233*283d5872SStefan Eichenberger  - |
234*283d5872SStefan Eichenberger    mdio {
235*283d5872SStefan Eichenberger        #address-cells = <1>;
236*283d5872SStefan Eichenberger        #size-cells = <0>;
237*283d5872SStefan Eichenberger
238*283d5872SStefan Eichenberger        ethernet-phy@7 {
239*283d5872SStefan Eichenberger            compatible = "ethernet-phy-id0022.1610";
240*283d5872SStefan Eichenberger            reg = <7>;
241*283d5872SStefan Eichenberger            rxc-skew-ps = <3000>;
242*283d5872SStefan Eichenberger            rxdv-skew-ps = <0>;
243*283d5872SStefan Eichenberger            txc-skew-ps = <3000>;
244*283d5872SStefan Eichenberger            txen-skew-ps = <0>;
245*283d5872SStefan Eichenberger        };
246*283d5872SStefan Eichenberger
247*283d5872SStefan Eichenberger        ethernet-phy@9 {
248*283d5872SStefan Eichenberger            compatible = "ethernet-phy-id0022.1640";
249*283d5872SStefan Eichenberger            reg = <9>;
250*283d5872SStefan Eichenberger            rxc-skew-psec = <(-100)>;
251*283d5872SStefan Eichenberger            txc-skew-psec = <(-100)>;
252*283d5872SStefan Eichenberger        };
253*283d5872SStefan Eichenberger    };
254