xref: /linux/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml (revision 64b14a184e83eb62ea0615e31a409956049d40e7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek STAR Ethernet MAC Controller
8
9maintainers:
10  - Bartosz Golaszewski <bgolaszewski@baylibre.com>
11
12description:
13  This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
14  It's compliant with 802.3 standards and supports half- and full-duplex
15  modes with flow-control as well as CRC offloading and VLAN tags.
16
17allOf:
18  - $ref: "ethernet-controller.yaml#"
19
20properties:
21  compatible:
22    enum:
23      - mediatek,mt8516-eth
24      - mediatek,mt8518-eth
25      - mediatek,mt8175-eth
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    minItems: 3
35    maxItems: 3
36
37  clock-names:
38    additionalItems: false
39    items:
40      - const: core
41      - const: reg
42      - const: trans
43
44  mediatek,pericfg:
45    $ref: /schemas/types.yaml#/definitions/phandle
46    description:
47      Phandle to the device containing the PERICFG register range. This is used
48      to control the MII mode.
49
50  mdio:
51    $ref: mdio.yaml#
52    unevaluatedProperties: false
53
54required:
55  - compatible
56  - reg
57  - interrupts
58  - clocks
59  - clock-names
60  - mediatek,pericfg
61  - phy-handle
62
63unevaluatedProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/interrupt-controller/arm-gic.h>
68    #include <dt-bindings/clock/mt8516-clk.h>
69
70    ethernet: ethernet@11180000 {
71        compatible = "mediatek,mt8516-eth";
72        reg = <0x11180000 0x1000>;
73        mediatek,pericfg = <&pericfg>;
74        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
75        clocks = <&topckgen CLK_TOP_RG_ETH>,
76                 <&topckgen CLK_TOP_66M_ETH>,
77                 <&topckgen CLK_TOP_133M_ETH>;
78        clock-names = "core", "reg", "trans";
79        phy-handle = <&eth_phy>;
80        phy-mode = "rmii";
81
82        mdio {
83            #address-cells = <1>;
84            #size-cells = <0>;
85
86            eth_phy: ethernet-phy@0 {
87                reg = <0>;
88            };
89        };
90    };
91