xref: /linux/Documentation/devicetree/bindings/net/mediatek,net.yaml (revision bba2c3615bd6cfee7456d1130f2e6b01b3f4e9ba) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7621-eth
23      - mediatek,mt7622-eth
24      - mediatek,mt7629-eth
25      - mediatek,mt7981-eth
26      - mediatek,mt7986-eth
27      - mediatek,mt7988-eth
28      - ralink,rt5350-eth
29
30  reg:
31    maxItems: 1
32
33  clocks:
34    minItems: 2
35    maxItems: 24
36
37  clock-names:
38    minItems: 2
39    maxItems: 24
40
41  interrupts:
42    minItems: 1
43    maxItems: 8
44
45  interrupt-names:
46    minItems: 1
47    items:
48      - const: fe0
49      - const: fe1
50      - const: fe2
51      - const: fe3
52      - const: pdma0
53      - const: pdma1
54      - const: pdma2
55      - const: pdma3
56
57  power-domains:
58    maxItems: 1
59
60  resets:
61    maxItems: 3
62
63  reset-names:
64    items:
65      - const: fe
66      - const: gmac
67      - const: ppe
68
69  sram:
70    maxItems: 1
71
72  mediatek,ethsys:
73    $ref: /schemas/types.yaml#/definitions/phandle
74    description:
75      Phandle to the syscon node that handles the port setup.
76
77  cci-control-port: true
78
79  mediatek,hifsys:
80    $ref: /schemas/types.yaml#/definitions/phandle
81    description:
82      Phandle to the mediatek hifsys controller used to provide various clocks
83      and reset to the system.
84
85  mediatek,infracfg:
86    $ref: /schemas/types.yaml#/definitions/phandle
87    description:
88      Phandle to the syscon node that handles the path from GMAC to
89      PHY variants.
90
91  mediatek,pcie-mirror:
92    $ref: /schemas/types.yaml#/definitions/phandle
93    description:
94      Phandle to the mediatek pcie-mirror controller.
95
96  mediatek,pctl:
97    $ref: /schemas/types.yaml#/definitions/phandle
98    description:
99      Phandle to the syscon node that handles the ports slew rate and
100      driver current.
101
102  mediatek,sgmiisys:
103    $ref: /schemas/types.yaml#/definitions/phandle-array
104    minItems: 1
105    maxItems: 2
106    items:
107      maxItems: 1
108    description:
109      A list of phandle to the syscon node that handles the SGMII setup which is required for
110      those SoCs equipped with SGMII.
111
112  mediatek,wed:
113    $ref: /schemas/types.yaml#/definitions/phandle-array
114    minItems: 1
115    maxItems: 2
116    items:
117      maxItems: 1
118    description:
119      List of phandles to wireless ethernet dispatch nodes.
120
121  mediatek,wed-pcie:
122    $ref: /schemas/types.yaml#/definitions/phandle
123    description:
124      Phandle to the mediatek wed-pcie controller.
125
126  dma-coherent: true
127
128  mdio-bus:
129    $ref: mdio.yaml#
130    unevaluatedProperties: false
131
132  "#address-cells":
133    const: 1
134
135  "#size-cells":
136    const: 0
137
138allOf:
139  - $ref: ethernet-controller.yaml#
140  - if:
141      properties:
142        compatible:
143          contains:
144            enum:
145              - mediatek,mt2701-eth
146              - mediatek,mt7623-eth
147    then:
148      properties:
149        interrupts:
150          minItems: 3
151          maxItems: 3
152
153        interrupt-names:
154          minItems: 3
155          maxItems: 3
156
157        clocks:
158          minItems: 4
159          maxItems: 4
160
161        clock-names:
162          items:
163            - const: ethif
164            - const: esw
165            - const: gp1
166            - const: gp2
167
168        sram: false
169
170        mediatek,infracfg: false
171
172        mediatek,wed: false
173
174        mediatek,wed-pcie: false
175    else:
176      properties:
177        mediatek,pctl: false
178
179  - if:
180      properties:
181        compatible:
182          contains:
183            enum:
184              - mediatek,mt7621-eth
185    then:
186      properties:
187        interrupts:
188          maxItems: 1
189
190        interrupt-names:
191          maxItems: 1
192
193        clocks:
194          minItems: 2
195          maxItems: 2
196
197        clock-names:
198          items:
199            - const: ethif
200            - const: fe
201
202        sram: false
203
204        mediatek,infracfg: false
205
206        mediatek,wed: false
207
208        mediatek,wed-pcie: false
209
210  - if:
211      properties:
212        compatible:
213          contains:
214            const: mediatek,mt7622-eth
215    then:
216      properties:
217        interrupts:
218          minItems: 3
219          maxItems: 3
220
221        interrupt-names:
222          minItems: 3
223          maxItems: 3
224
225        clocks:
226          minItems: 11
227          maxItems: 11
228
229        clock-names:
230          items:
231            - const: ethif
232            - const: esw
233            - const: gp0
234            - const: gp1
235            - const: gp2
236            - const: sgmii_tx250m
237            - const: sgmii_rx250m
238            - const: sgmii_cdr_ref
239            - const: sgmii_cdr_fb
240            - const: sgmii_ck
241            - const: eth2pll
242
243        sram: false
244
245        mediatek,infracfg: false
246
247        mediatek,sgmiisys:
248          minItems: 1
249          maxItems: 1
250
251        mediatek,wed:
252          minItems: 2
253
254        mediatek,wed-pcie: false
255    else:
256      properties:
257        mediatek,pcie-mirror: false
258
259  - if:
260      properties:
261        compatible:
262          contains:
263            const: mediatek,mt7629-eth
264    then:
265      properties:
266        interrupts:
267          minItems: 3
268          maxItems: 3
269
270        interrupt-names:
271          minItems: 3
272          maxItems: 3
273
274        clocks:
275          minItems: 17
276          maxItems: 17
277
278        clock-names:
279          items:
280            - const: ethif
281            - const: sgmiitop
282            - const: esw
283            - const: gp0
284            - const: gp1
285            - const: gp2
286            - const: fe
287            - const: sgmii_tx250m
288            - const: sgmii_rx250m
289            - const: sgmii_cdr_ref
290            - const: sgmii_cdr_fb
291            - const: sgmii2_tx250m
292            - const: sgmii2_rx250m
293            - const: sgmii2_cdr_ref
294            - const: sgmii2_cdr_fb
295            - const: sgmii_ck
296            - const: eth2pll
297
298        sram: false
299
300        mediatek,sgmiisys:
301          minItems: 2
302          maxItems: 2
303
304        mediatek,wed: false
305
306        mediatek,wed-pcie: false
307
308  - if:
309      properties:
310        compatible:
311          contains:
312            const: mediatek,mt7981-eth
313    then:
314      properties:
315        interrupts:
316          minItems: 8
317
318        interrupt-names:
319          minItems: 8
320
321        clocks:
322          minItems: 15
323          maxItems: 15
324
325        clock-names:
326          items:
327            - const: fe
328            - const: gp2
329            - const: gp1
330            - const: wocpu0
331            - const: sgmii_ck
332            - const: sgmii_tx250m
333            - const: sgmii_rx250m
334            - const: sgmii_cdr_ref
335            - const: sgmii_cdr_fb
336            - const: sgmii2_tx250m
337            - const: sgmii2_rx250m
338            - const: sgmii2_cdr_ref
339            - const: sgmii2_cdr_fb
340            - const: netsys0
341            - const: netsys1
342
343        mediatek,sgmiisys:
344          minItems: 2
345          maxItems: 2
346
347        mediatek,wed:
348          maxItems: 1
349
350  - if:
351      properties:
352        compatible:
353          contains:
354            const: mediatek,mt7986-eth
355    then:
356      properties:
357        interrupts:
358          minItems: 8
359
360        interrupt-names:
361          minItems: 8
362
363        clocks:
364          minItems: 15
365          maxItems: 15
366
367        clock-names:
368          items:
369            - const: fe
370            - const: gp2
371            - const: gp1
372            - const: wocpu1
373            - const: wocpu0
374            - const: sgmii_tx250m
375            - const: sgmii_rx250m
376            - const: sgmii_cdr_ref
377            - const: sgmii_cdr_fb
378            - const: sgmii2_tx250m
379            - const: sgmii2_rx250m
380            - const: sgmii2_cdr_ref
381            - const: sgmii2_cdr_fb
382            - const: netsys0
383            - const: netsys1
384
385        mediatek,infracfg: false
386
387        mediatek,sgmiisys:
388          minItems: 2
389          maxItems: 2
390
391        mediatek,wed:
392          minItems: 2
393
394  - if:
395      properties:
396        compatible:
397          contains:
398            const: mediatek,mt7988-eth
399    then:
400      properties:
401        interrupts:
402          minItems: 8
403
404        interrupt-names:
405          minItems: 8
406
407        clocks:
408          minItems: 24
409          maxItems: 24
410
411        clock-names:
412          items:
413            - const: crypto
414            - const: fe
415            - const: gp2
416            - const: gp1
417            - const: gp3
418            - const: ethwarp_wocpu2
419            - const: ethwarp_wocpu1
420            - const: ethwarp_wocpu0
421            - const: esw
422            - const: top_eth_gmii_sel
423            - const: top_eth_refck_50m_sel
424            - const: top_eth_sys_200m_sel
425            - const: top_eth_sys_sel
426            - const: top_eth_xgmii_sel
427            - const: top_eth_mii_sel
428            - const: top_netsys_sel
429            - const: top_netsys_500m_sel
430            - const: top_netsys_pao_2x_sel
431            - const: top_netsys_sync_250m_sel
432            - const: top_netsys_ppefb_250m_sel
433            - const: top_netsys_warp_sel
434            - const: xgp1
435            - const: xgp2
436            - const: xgp3
437
438        mediatek,wed:
439          minItems: 2
440
441  - if:
442      properties:
443        compatible:
444          contains:
445            const: ralink,rt5350-eth
446    then:
447      properties:
448        mediatek,wed:
449          minItems: 2
450
451patternProperties:
452  "^mac@[0-2]$":
453    type: object
454    unevaluatedProperties: false
455    allOf:
456      - $ref: ethernet-controller.yaml#
457    description:
458      Ethernet MAC node
459    properties:
460      compatible:
461        const: mediatek,eth-mac
462
463      reg:
464        maxItems: 1
465
466    required:
467      - reg
468      - compatible
469
470required:
471  - compatible
472  - reg
473  - interrupts
474  - clocks
475  - clock-names
476  - mediatek,ethsys
477
478unevaluatedProperties: false
479
480examples:
481  - |
482    #include <dt-bindings/interrupt-controller/arm-gic.h>
483    #include <dt-bindings/interrupt-controller/irq.h>
484    #include <dt-bindings/clock/mt7622-clk.h>
485    #include <dt-bindings/power/mt7622-power.h>
486
487    soc {
488      #address-cells = <2>;
489      #size-cells = <2>;
490
491      ethernet: ethernet@1b100000 {
492        compatible = "mediatek,mt7622-eth";
493        reg = <0 0x1b100000 0 0x20000>;
494        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
495                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
496                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
497        clocks = <&topckgen CLK_TOP_ETH_SEL>,
498                 <&ethsys CLK_ETH_ESW_EN>,
499                 <&ethsys CLK_ETH_GP0_EN>,
500                 <&ethsys CLK_ETH_GP1_EN>,
501                 <&ethsys CLK_ETH_GP2_EN>,
502                 <&sgmiisys CLK_SGMII_TX250M_EN>,
503                 <&sgmiisys CLK_SGMII_RX250M_EN>,
504                 <&sgmiisys CLK_SGMII_CDR_REF>,
505                 <&sgmiisys CLK_SGMII_CDR_FB>,
506                 <&topckgen CLK_TOP_SGMIIPLL>,
507                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
508        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
509                      "sgmii_tx250m", "sgmii_rx250m",
510                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
511                      "eth2pll";
512        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
513        mediatek,ethsys = <&ethsys>;
514        mediatek,sgmiisys = <&sgmiisys>;
515        cci-control-port = <&cci_control2>;
516        mediatek,pcie-mirror = <&pcie_mirror>;
517        mediatek,hifsys = <&hifsys>;
518        dma-coherent;
519
520        #address-cells = <1>;
521        #size-cells = <0>;
522
523        mdio0: mdio-bus {
524          #address-cells = <1>;
525          #size-cells = <0>;
526
527          phy0: ethernet-phy@0 {
528            reg = <0>;
529          };
530
531          phy1: ethernet-phy@1 {
532            reg = <1>;
533          };
534        };
535
536        gmac0: mac@0 {
537          compatible = "mediatek,eth-mac";
538          phy-mode = "rgmii";
539          phy-handle = <&phy0>;
540          reg = <0>;
541        };
542
543        gmac1: mac@1 {
544          compatible = "mediatek,eth-mac";
545          phy-mode = "rgmii";
546          phy-handle = <&phy1>;
547          reg = <1>;
548        };
549      };
550    };
551
552  - |
553    #include <dt-bindings/interrupt-controller/arm-gic.h>
554    #include <dt-bindings/interrupt-controller/irq.h>
555    #include <dt-bindings/clock/mt7622-clk.h>
556
557    soc {
558      #address-cells = <2>;
559      #size-cells = <2>;
560
561      eth: ethernet@15100000 {
562        #define CLK_ETH_FE_EN               0
563        #define CLK_ETH_WOCPU1_EN           3
564        #define CLK_ETH_WOCPU0_EN           4
565        #define CLK_TOP_NETSYS_SEL          43
566        #define CLK_TOP_NETSYS_500M_SEL     44
567        #define CLK_TOP_NETSYS_2X_SEL       46
568        #define CLK_TOP_SGM_325M_SEL        47
569        #define CLK_APMIXED_NET2PLL         1
570        #define CLK_APMIXED_SGMPLL          3
571
572        compatible = "mediatek,mt7986-eth";
573        reg = <0 0x15100000 0 0x80000>;
574        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
575                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
576                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
577                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
578                     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
579                     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
580                     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
581                     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
582        clocks = <&ethsys CLK_ETH_FE_EN>,
583                 <&ethsys CLK_ETH_GP2_EN>,
584                 <&ethsys CLK_ETH_GP1_EN>,
585                 <&ethsys CLK_ETH_WOCPU1_EN>,
586                 <&ethsys CLK_ETH_WOCPU0_EN>,
587                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
588                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
589                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
590                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
591                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
592                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
593                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
594                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
595                 <&topckgen CLK_TOP_NETSYS_SEL>,
596                 <&topckgen CLK_TOP_NETSYS_SEL>;
597        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
598                      "sgmii_tx250m", "sgmii_rx250m",
599                      "sgmii_cdr_ref", "sgmii_cdr_fb",
600                      "sgmii2_tx250m", "sgmii2_rx250m",
601                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
602                      "netsys0", "netsys1";
603        mediatek,ethsys = <&ethsys>;
604        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
605        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
606                          <&topckgen CLK_TOP_SGM_325M_SEL>;
607        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
608                                 <&apmixedsys CLK_APMIXED_SGMPLL>;
609
610        #address-cells = <1>;
611        #size-cells = <0>;
612
613        mdio: mdio-bus {
614          #address-cells = <1>;
615          #size-cells = <0>;
616
617          phy5: ethernet-phy@0 {
618            compatible = "ethernet-phy-id67c9.de0a";
619            phy-mode = "2500base-x";
620            reset-gpios = <&pio 6 1>;
621            reset-deassert-us = <20000>;
622            reg = <5>;
623          };
624
625          phy6: ethernet-phy@1 {
626            compatible = "ethernet-phy-id67c9.de0a";
627            phy-mode = "2500base-x";
628            reg = <6>;
629          };
630        };
631
632        mac0: mac@0 {
633          compatible = "mediatek,eth-mac";
634          phy-mode = "2500base-x";
635          phy-handle = <&phy5>;
636          reg = <0>;
637        };
638
639        mac1: mac@1 {
640          compatible = "mediatek,eth-mac";
641          phy-mode = "2500base-x";
642          phy-handle = <&phy6>;
643          reg = <1>;
644        };
645      };
646    };
647