xref: /linux/Documentation/devicetree/bindings/net/mediatek,net.yaml (revision 6aac2aa2dfae38b60f22c3dfe4103ceefbe2d761) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7621-eth
23      - mediatek,mt7622-eth
24      - mediatek,mt7629-eth
25      - mediatek,mt7981-eth
26      - mediatek,mt7986-eth
27      - mediatek,mt7988-eth
28      - ralink,rt5350-eth
29
30  reg:
31    maxItems: 1
32
33  clocks:
34    minItems: 2
35    maxItems: 24
36
37  clock-names:
38    minItems: 2
39    maxItems: 24
40
41  interrupts:
42    minItems: 1
43    maxItems: 8
44
45  interrupt-names:
46    minItems: 1
47    items:
48      - const: fe0
49      - const: fe1
50      - const: fe2
51      - const: fe3
52      - const: pdma0
53      - const: pdma1
54      - const: pdma2
55      - const: pdma3
56
57  power-domains:
58    maxItems: 1
59
60  resets:
61    maxItems: 3
62
63  reset-names:
64    items:
65      - const: fe
66      - const: gmac
67      - const: ppe
68
69  sram:
70    $ref: /schemas/types.yaml#/definitions/phandle
71    description: phandle to mmio SRAM
72
73  mediatek,ethsys:
74    $ref: /schemas/types.yaml#/definitions/phandle
75    description:
76      Phandle to the syscon node that handles the port setup.
77
78  cci-control-port: true
79
80  mediatek,hifsys:
81    $ref: /schemas/types.yaml#/definitions/phandle
82    description:
83      Phandle to the mediatek hifsys controller used to provide various clocks
84      and reset to the system.
85
86  mediatek,infracfg:
87    $ref: /schemas/types.yaml#/definitions/phandle
88    description:
89      Phandle to the syscon node that handles the path from GMAC to
90      PHY variants.
91
92  mediatek,pcie-mirror:
93    $ref: /schemas/types.yaml#/definitions/phandle
94    description:
95      Phandle to the mediatek pcie-mirror controller.
96
97  mediatek,pctl:
98    $ref: /schemas/types.yaml#/definitions/phandle
99    description:
100      Phandle to the syscon node that handles the ports slew rate and
101      driver current.
102
103  mediatek,sgmiisys:
104    $ref: /schemas/types.yaml#/definitions/phandle-array
105    minItems: 1
106    maxItems: 2
107    items:
108      maxItems: 1
109    description:
110      A list of phandle to the syscon node that handles the SGMII setup which is required for
111      those SoCs equipped with SGMII.
112
113  mediatek,wed:
114    $ref: /schemas/types.yaml#/definitions/phandle-array
115    minItems: 1
116    maxItems: 2
117    items:
118      maxItems: 1
119    description:
120      List of phandles to wireless ethernet dispatch nodes.
121
122  mediatek,wed-pcie:
123    $ref: /schemas/types.yaml#/definitions/phandle
124    description:
125      Phandle to the mediatek wed-pcie controller.
126
127  dma-coherent: true
128
129  mdio-bus:
130    $ref: mdio.yaml#
131    unevaluatedProperties: false
132
133  "#address-cells":
134    const: 1
135
136  "#size-cells":
137    const: 0
138
139allOf:
140  - $ref: ethernet-controller.yaml#
141  - if:
142      properties:
143        compatible:
144          contains:
145            enum:
146              - mediatek,mt2701-eth
147              - mediatek,mt7623-eth
148    then:
149      properties:
150        interrupts:
151          minItems: 3
152          maxItems: 3
153
154        interrupt-names:
155          minItems: 3
156          maxItems: 3
157
158        clocks:
159          minItems: 4
160          maxItems: 4
161
162        clock-names:
163          items:
164            - const: ethif
165            - const: esw
166            - const: gp1
167            - const: gp2
168
169        sram: false
170
171        mediatek,infracfg: false
172
173        mediatek,wed: false
174
175        mediatek,wed-pcie: false
176    else:
177      properties:
178        mediatek,pctl: false
179
180  - if:
181      properties:
182        compatible:
183          contains:
184            enum:
185              - mediatek,mt7621-eth
186    then:
187      properties:
188        interrupts:
189          maxItems: 1
190
191        interrupt-names:
192          maxItems: 1
193
194        clocks:
195          minItems: 2
196          maxItems: 2
197
198        clock-names:
199          items:
200            - const: ethif
201            - const: fe
202
203        sram: false
204
205        mediatek,infracfg: false
206
207        mediatek,wed: false
208
209        mediatek,wed-pcie: false
210
211  - if:
212      properties:
213        compatible:
214          contains:
215            const: mediatek,mt7622-eth
216    then:
217      properties:
218        interrupts:
219          minItems: 3
220          maxItems: 3
221
222        interrupt-names:
223          minItems: 3
224          maxItems: 3
225
226        clocks:
227          minItems: 11
228          maxItems: 11
229
230        clock-names:
231          items:
232            - const: ethif
233            - const: esw
234            - const: gp0
235            - const: gp1
236            - const: gp2
237            - const: sgmii_tx250m
238            - const: sgmii_rx250m
239            - const: sgmii_cdr_ref
240            - const: sgmii_cdr_fb
241            - const: sgmii_ck
242            - const: eth2pll
243
244        sram: false
245
246        mediatek,infracfg: false
247
248        mediatek,sgmiisys:
249          minItems: 1
250          maxItems: 1
251
252        mediatek,wed:
253          minItems: 2
254
255        mediatek,wed-pcie: false
256    else:
257      properties:
258        mediatek,pcie-mirror: false
259
260  - if:
261      properties:
262        compatible:
263          contains:
264            const: mediatek,mt7629-eth
265    then:
266      properties:
267        interrupts:
268          minItems: 3
269          maxItems: 3
270
271        interrupt-names:
272          minItems: 3
273          maxItems: 3
274
275        clocks:
276          minItems: 17
277          maxItems: 17
278
279        clock-names:
280          items:
281            - const: ethif
282            - const: sgmiitop
283            - const: esw
284            - const: gp0
285            - const: gp1
286            - const: gp2
287            - const: fe
288            - const: sgmii_tx250m
289            - const: sgmii_rx250m
290            - const: sgmii_cdr_ref
291            - const: sgmii_cdr_fb
292            - const: sgmii2_tx250m
293            - const: sgmii2_rx250m
294            - const: sgmii2_cdr_ref
295            - const: sgmii2_cdr_fb
296            - const: sgmii_ck
297            - const: eth2pll
298
299        sram: false
300
301        mediatek,sgmiisys:
302          minItems: 2
303          maxItems: 2
304
305        mediatek,wed: false
306
307        mediatek,wed-pcie: false
308
309  - if:
310      properties:
311        compatible:
312          contains:
313            const: mediatek,mt7981-eth
314    then:
315      properties:
316        interrupts:
317          minItems: 8
318
319        interrupt-names:
320          minItems: 8
321
322        clocks:
323          minItems: 15
324          maxItems: 15
325
326        clock-names:
327          items:
328            - const: fe
329            - const: gp2
330            - const: gp1
331            - const: wocpu0
332            - const: sgmii_ck
333            - const: sgmii_tx250m
334            - const: sgmii_rx250m
335            - const: sgmii_cdr_ref
336            - const: sgmii_cdr_fb
337            - const: sgmii2_tx250m
338            - const: sgmii2_rx250m
339            - const: sgmii2_cdr_ref
340            - const: sgmii2_cdr_fb
341            - const: netsys0
342            - const: netsys1
343
344        mediatek,sgmiisys:
345          minItems: 2
346          maxItems: 2
347
348        mediatek,wed:
349          maxItems: 1
350
351  - if:
352      properties:
353        compatible:
354          contains:
355            const: mediatek,mt7986-eth
356    then:
357      properties:
358        interrupts:
359          minItems: 8
360
361        interrupt-names:
362          minItems: 8
363
364        clocks:
365          minItems: 15
366          maxItems: 15
367
368        clock-names:
369          items:
370            - const: fe
371            - const: gp2
372            - const: gp1
373            - const: wocpu1
374            - const: wocpu0
375            - const: sgmii_tx250m
376            - const: sgmii_rx250m
377            - const: sgmii_cdr_ref
378            - const: sgmii_cdr_fb
379            - const: sgmii2_tx250m
380            - const: sgmii2_rx250m
381            - const: sgmii2_cdr_ref
382            - const: sgmii2_cdr_fb
383            - const: netsys0
384            - const: netsys1
385
386        mediatek,infracfg: false
387
388        mediatek,sgmiisys:
389          minItems: 2
390          maxItems: 2
391
392        mediatek,wed:
393          minItems: 2
394
395  - if:
396      properties:
397        compatible:
398          contains:
399            const: mediatek,mt7988-eth
400    then:
401      properties:
402        interrupts:
403          minItems: 8
404
405        interrupt-names:
406          minItems: 8
407
408        clocks:
409          minItems: 24
410          maxItems: 24
411
412        clock-names:
413          items:
414            - const: crypto
415            - const: fe
416            - const: gp2
417            - const: gp1
418            - const: gp3
419            - const: ethwarp_wocpu2
420            - const: ethwarp_wocpu1
421            - const: ethwarp_wocpu0
422            - const: esw
423            - const: top_eth_gmii_sel
424            - const: top_eth_refck_50m_sel
425            - const: top_eth_sys_200m_sel
426            - const: top_eth_sys_sel
427            - const: top_eth_xgmii_sel
428            - const: top_eth_mii_sel
429            - const: top_netsys_sel
430            - const: top_netsys_500m_sel
431            - const: top_netsys_pao_2x_sel
432            - const: top_netsys_sync_250m_sel
433            - const: top_netsys_ppefb_250m_sel
434            - const: top_netsys_warp_sel
435            - const: xgp1
436            - const: xgp2
437            - const: xgp3
438
439        mediatek,wed:
440          minItems: 2
441
442  - if:
443      properties:
444        compatible:
445          contains:
446            const: ralink,rt5350-eth
447    then:
448      properties:
449        mediatek,wed:
450          minItems: 2
451
452patternProperties:
453  "^mac@[0-2]$":
454    type: object
455    unevaluatedProperties: false
456    allOf:
457      - $ref: ethernet-controller.yaml#
458    description:
459      Ethernet MAC node
460    properties:
461      compatible:
462        const: mediatek,eth-mac
463
464      reg:
465        maxItems: 1
466
467    required:
468      - reg
469      - compatible
470
471required:
472  - compatible
473  - reg
474  - interrupts
475  - clocks
476  - clock-names
477  - mediatek,ethsys
478
479unevaluatedProperties: false
480
481examples:
482  - |
483    #include <dt-bindings/interrupt-controller/arm-gic.h>
484    #include <dt-bindings/interrupt-controller/irq.h>
485    #include <dt-bindings/clock/mt7622-clk.h>
486    #include <dt-bindings/power/mt7622-power.h>
487
488    soc {
489      #address-cells = <2>;
490      #size-cells = <2>;
491
492      ethernet: ethernet@1b100000 {
493        compatible = "mediatek,mt7622-eth";
494        reg = <0 0x1b100000 0 0x20000>;
495        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
496                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
497                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
498        clocks = <&topckgen CLK_TOP_ETH_SEL>,
499                 <&ethsys CLK_ETH_ESW_EN>,
500                 <&ethsys CLK_ETH_GP0_EN>,
501                 <&ethsys CLK_ETH_GP1_EN>,
502                 <&ethsys CLK_ETH_GP2_EN>,
503                 <&sgmiisys CLK_SGMII_TX250M_EN>,
504                 <&sgmiisys CLK_SGMII_RX250M_EN>,
505                 <&sgmiisys CLK_SGMII_CDR_REF>,
506                 <&sgmiisys CLK_SGMII_CDR_FB>,
507                 <&topckgen CLK_TOP_SGMIIPLL>,
508                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
509        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
510                      "sgmii_tx250m", "sgmii_rx250m",
511                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
512                      "eth2pll";
513        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
514        mediatek,ethsys = <&ethsys>;
515        mediatek,sgmiisys = <&sgmiisys>;
516        cci-control-port = <&cci_control2>;
517        mediatek,pcie-mirror = <&pcie_mirror>;
518        mediatek,hifsys = <&hifsys>;
519        dma-coherent;
520
521        #address-cells = <1>;
522        #size-cells = <0>;
523
524        mdio0: mdio-bus {
525          #address-cells = <1>;
526          #size-cells = <0>;
527
528          phy0: ethernet-phy@0 {
529            reg = <0>;
530          };
531
532          phy1: ethernet-phy@1 {
533            reg = <1>;
534          };
535        };
536
537        gmac0: mac@0 {
538          compatible = "mediatek,eth-mac";
539          phy-mode = "rgmii";
540          phy-handle = <&phy0>;
541          reg = <0>;
542        };
543
544        gmac1: mac@1 {
545          compatible = "mediatek,eth-mac";
546          phy-mode = "rgmii";
547          phy-handle = <&phy1>;
548          reg = <1>;
549        };
550      };
551    };
552
553  - |
554    #include <dt-bindings/interrupt-controller/arm-gic.h>
555    #include <dt-bindings/interrupt-controller/irq.h>
556    #include <dt-bindings/clock/mt7622-clk.h>
557
558    soc {
559      #address-cells = <2>;
560      #size-cells = <2>;
561
562      eth: ethernet@15100000 {
563        #define CLK_ETH_FE_EN               0
564        #define CLK_ETH_WOCPU1_EN           3
565        #define CLK_ETH_WOCPU0_EN           4
566        #define CLK_TOP_NETSYS_SEL          43
567        #define CLK_TOP_NETSYS_500M_SEL     44
568        #define CLK_TOP_NETSYS_2X_SEL       46
569        #define CLK_TOP_SGM_325M_SEL        47
570        #define CLK_APMIXED_NET2PLL         1
571        #define CLK_APMIXED_SGMPLL          3
572
573        compatible = "mediatek,mt7986-eth";
574        reg = <0 0x15100000 0 0x80000>;
575        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
576                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
577                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
578                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
579                     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
580                     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
581                     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
582                     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
583        clocks = <&ethsys CLK_ETH_FE_EN>,
584                 <&ethsys CLK_ETH_GP2_EN>,
585                 <&ethsys CLK_ETH_GP1_EN>,
586                 <&ethsys CLK_ETH_WOCPU1_EN>,
587                 <&ethsys CLK_ETH_WOCPU0_EN>,
588                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
589                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
590                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
591                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
592                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
593                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
594                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
595                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
596                 <&topckgen CLK_TOP_NETSYS_SEL>,
597                 <&topckgen CLK_TOP_NETSYS_SEL>;
598        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
599                      "sgmii_tx250m", "sgmii_rx250m",
600                      "sgmii_cdr_ref", "sgmii_cdr_fb",
601                      "sgmii2_tx250m", "sgmii2_rx250m",
602                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
603                      "netsys0", "netsys1";
604        mediatek,ethsys = <&ethsys>;
605        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
606        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
607                          <&topckgen CLK_TOP_SGM_325M_SEL>;
608        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
609                                 <&apmixedsys CLK_APMIXED_SGMPLL>;
610
611        #address-cells = <1>;
612        #size-cells = <0>;
613
614        mdio: mdio-bus {
615          #address-cells = <1>;
616          #size-cells = <0>;
617
618          phy5: ethernet-phy@0 {
619            compatible = "ethernet-phy-id67c9.de0a";
620            phy-mode = "2500base-x";
621            reset-gpios = <&pio 6 1>;
622            reset-deassert-us = <20000>;
623            reg = <5>;
624          };
625
626          phy6: ethernet-phy@1 {
627            compatible = "ethernet-phy-id67c9.de0a";
628            phy-mode = "2500base-x";
629            reg = <6>;
630          };
631        };
632
633        mac0: mac@0 {
634          compatible = "mediatek,eth-mac";
635          phy-mode = "2500base-x";
636          phy-handle = <&phy5>;
637          reg = <0>;
638        };
639
640        mac1: mac@1 {
641          compatible = "mediatek,eth-mac";
642          phy-mode = "2500base-x";
643          phy-handle = <&phy6>;
644          reg = <1>;
645        };
646      };
647    };
648