xref: /linux/Documentation/devicetree/bindings/net/mediatek,net.yaml (revision 7e062cda7d90543ac8c7700fc7c5527d0c0f22ad) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7622-eth
23      - mediatek,mt7629-eth
24      - mediatek,mt7986-eth
25      - ralink,rt5350-eth
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    minItems: 3
32    maxItems: 4
33
34  power-domains:
35    maxItems: 1
36
37  resets:
38    maxItems: 3
39
40  reset-names:
41    items:
42      - const: fe
43      - const: gmac
44      - const: ppe
45
46  mediatek,ethsys:
47    $ref: /schemas/types.yaml#/definitions/phandle
48    description:
49      Phandle to the syscon node that handles the port setup.
50
51  cci-control-port: true
52
53  mediatek,hifsys:
54    $ref: /schemas/types.yaml#/definitions/phandle
55    description:
56      Phandle to the mediatek hifsys controller used to provide various clocks
57      and reset to the system.
58
59  mediatek,sgmiisys:
60    $ref: /schemas/types.yaml#/definitions/phandle-array
61    minItems: 1
62    maxItems: 2
63    items:
64      maxItems: 1
65    description:
66      A list of phandle to the syscon node that handles the SGMII setup which is required for
67      those SoCs equipped with SGMII.
68
69  dma-coherent: true
70
71  mdio-bus:
72    $ref: mdio.yaml#
73    unevaluatedProperties: false
74
75  "#address-cells":
76    const: 1
77
78  "#size-cells":
79    const: 0
80
81allOf:
82  - $ref: "ethernet-controller.yaml#"
83  - if:
84      properties:
85        compatible:
86          contains:
87            enum:
88              - mediatek,mt2701-eth
89              - mediatek,mt7623-eth
90    then:
91      properties:
92        interrupts:
93          maxItems: 3
94
95        clocks:
96          minItems: 4
97          maxItems: 4
98
99        clock-names:
100          items:
101            - const: ethif
102            - const: esw
103            - const: gp1
104            - const: gp2
105
106        mediatek,pctl:
107          $ref: /schemas/types.yaml#/definitions/phandle
108          description:
109            Phandle to the syscon node that handles the ports slew rate and
110            driver current.
111
112  - if:
113      properties:
114        compatible:
115          contains:
116            const: mediatek,mt7622-eth
117    then:
118      properties:
119        interrupts:
120          maxItems: 3
121
122        clocks:
123          minItems: 11
124          maxItems: 11
125
126        clock-names:
127          items:
128            - const: ethif
129            - const: esw
130            - const: gp0
131            - const: gp1
132            - const: gp2
133            - const: sgmii_tx250m
134            - const: sgmii_rx250m
135            - const: sgmii_cdr_ref
136            - const: sgmii_cdr_fb
137            - const: sgmii_ck
138            - const: eth2pll
139
140        mediatek,sgmiisys:
141          minItems: 1
142          maxItems: 1
143
144        mediatek,wed:
145          $ref: /schemas/types.yaml#/definitions/phandle-array
146          minItems: 2
147          maxItems: 2
148          items:
149            maxItems: 1
150          description:
151            List of phandles to wireless ethernet dispatch nodes.
152
153        mediatek,pcie-mirror:
154          $ref: /schemas/types.yaml#/definitions/phandle
155          description:
156            Phandle to the mediatek pcie-mirror controller.
157
158  - if:
159      properties:
160        compatible:
161          contains:
162            const: mediatek,mt7629-eth
163    then:
164      properties:
165        interrupts:
166          maxItems: 3
167
168        clocks:
169          minItems: 17
170          maxItems: 17
171
172        clock-names:
173          items:
174            - const: ethif
175            - const: sgmiitop
176            - const: esw
177            - const: gp0
178            - const: gp1
179            - const: gp2
180            - const: fe
181            - const: sgmii_tx250m
182            - const: sgmii_rx250m
183            - const: sgmii_cdr_ref
184            - const: sgmii_cdr_fb
185            - const: sgmii2_tx250m
186            - const: sgmii2_rx250m
187            - const: sgmii2_cdr_ref
188            - const: sgmii2_cdr_fb
189            - const: sgmii_ck
190            - const: eth2pll
191
192        mediatek,infracfg:
193          $ref: /schemas/types.yaml#/definitions/phandle
194          description:
195            Phandle to the syscon node that handles the path from GMAC to
196            PHY variants.
197
198        mediatek,sgmiisys:
199          minItems: 2
200          maxItems: 2
201
202  - if:
203      properties:
204        compatible:
205          contains:
206            const: mediatek,mt7986-eth
207    then:
208      properties:
209        interrupts:
210          minItems: 4
211
212        clocks:
213          minItems: 15
214          maxItems: 15
215
216        clock-names:
217          items:
218            - const: fe
219            - const: gp2
220            - const: gp1
221            - const: wocpu1
222            - const: wocpu0
223            - const: sgmii_tx250m
224            - const: sgmii_rx250m
225            - const: sgmii_cdr_ref
226            - const: sgmii_cdr_fb
227            - const: sgmii2_tx250m
228            - const: sgmii2_rx250m
229            - const: sgmii2_cdr_ref
230            - const: sgmii2_cdr_fb
231            - const: netsys0
232            - const: netsys1
233
234        mediatek,sgmiisys:
235          minItems: 2
236          maxItems: 2
237
238patternProperties:
239  "^mac@[0-1]$":
240    type: object
241    additionalProperties: false
242    allOf:
243      - $ref: ethernet-controller.yaml#
244    description:
245      Ethernet MAC node
246    properties:
247      compatible:
248        const: mediatek,eth-mac
249
250      reg:
251        maxItems: 1
252
253      phy-handle: true
254
255      phy-mode: true
256
257    required:
258      - reg
259      - compatible
260      - phy-handle
261
262required:
263  - compatible
264  - reg
265  - interrupts
266  - clocks
267  - clock-names
268  - mediatek,ethsys
269
270unevaluatedProperties: false
271
272examples:
273  - |
274    #include <dt-bindings/interrupt-controller/arm-gic.h>
275    #include <dt-bindings/interrupt-controller/irq.h>
276    #include <dt-bindings/clock/mt7622-clk.h>
277    #include <dt-bindings/power/mt7622-power.h>
278
279    soc {
280      #address-cells = <2>;
281      #size-cells = <2>;
282
283      ethernet: ethernet@1b100000 {
284        compatible = "mediatek,mt7622-eth";
285        reg = <0 0x1b100000 0 0x20000>;
286        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
287                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
288                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
289        clocks = <&topckgen CLK_TOP_ETH_SEL>,
290                 <&ethsys CLK_ETH_ESW_EN>,
291                 <&ethsys CLK_ETH_GP0_EN>,
292                 <&ethsys CLK_ETH_GP1_EN>,
293                 <&ethsys CLK_ETH_GP2_EN>,
294                 <&sgmiisys CLK_SGMII_TX250M_EN>,
295                 <&sgmiisys CLK_SGMII_RX250M_EN>,
296                 <&sgmiisys CLK_SGMII_CDR_REF>,
297                 <&sgmiisys CLK_SGMII_CDR_FB>,
298                 <&topckgen CLK_TOP_SGMIIPLL>,
299                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
300        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
301                      "sgmii_tx250m", "sgmii_rx250m",
302                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
303                      "eth2pll";
304        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
305        mediatek,ethsys = <&ethsys>;
306        mediatek,sgmiisys = <&sgmiisys>;
307        cci-control-port = <&cci_control2>;
308        mediatek,pcie-mirror = <&pcie_mirror>;
309        mediatek,hifsys = <&hifsys>;
310        dma-coherent;
311
312        #address-cells = <1>;
313        #size-cells = <0>;
314
315        mdio0: mdio-bus {
316          #address-cells = <1>;
317          #size-cells = <0>;
318
319          phy0: ethernet-phy@0 {
320            reg = <0>;
321          };
322
323          phy1: ethernet-phy@1 {
324            reg = <1>;
325          };
326        };
327
328        gmac0: mac@0 {
329          compatible = "mediatek,eth-mac";
330          phy-mode = "rgmii";
331          phy-handle = <&phy0>;
332          reg = <0>;
333        };
334
335        gmac1: mac@1 {
336          compatible = "mediatek,eth-mac";
337          phy-mode = "rgmii";
338          phy-handle = <&phy1>;
339          reg = <1>;
340        };
341      };
342    };
343
344  - |
345    #include <dt-bindings/interrupt-controller/arm-gic.h>
346    #include <dt-bindings/interrupt-controller/irq.h>
347    #include <dt-bindings/clock/mt7622-clk.h>
348
349    soc {
350      #address-cells = <2>;
351      #size-cells = <2>;
352
353      eth: ethernet@15100000 {
354        #define CLK_ETH_FE_EN               0
355        #define CLK_ETH_WOCPU1_EN           3
356        #define CLK_ETH_WOCPU0_EN           4
357        #define CLK_TOP_NETSYS_SEL          43
358        #define CLK_TOP_NETSYS_500M_SEL     44
359        #define CLK_TOP_NETSYS_2X_SEL       46
360        #define CLK_TOP_SGM_325M_SEL        47
361        #define CLK_APMIXED_NET2PLL         1
362        #define CLK_APMIXED_SGMPLL          3
363
364        compatible = "mediatek,mt7986-eth";
365        reg = <0 0x15100000 0 0x80000>;
366        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
367                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
368                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
369                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
370        clocks = <&ethsys CLK_ETH_FE_EN>,
371                 <&ethsys CLK_ETH_GP2_EN>,
372                 <&ethsys CLK_ETH_GP1_EN>,
373                 <&ethsys CLK_ETH_WOCPU1_EN>,
374                 <&ethsys CLK_ETH_WOCPU0_EN>,
375                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
376                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
377                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
378                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
379                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
380                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
381                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
382                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
383                 <&topckgen CLK_TOP_NETSYS_SEL>,
384                 <&topckgen CLK_TOP_NETSYS_SEL>;
385        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
386                      "sgmii_tx250m", "sgmii_rx250m",
387                      "sgmii_cdr_ref", "sgmii_cdr_fb",
388                      "sgmii2_tx250m", "sgmii2_rx250m",
389                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
390                      "netsys0", "netsys1";
391        mediatek,ethsys = <&ethsys>;
392        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
393        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
394                          <&topckgen CLK_TOP_SGM_325M_SEL>;
395        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
396                                 <&apmixedsys CLK_APMIXED_SGMPLL>;
397
398        #address-cells = <1>;
399        #size-cells = <0>;
400
401        mdio: mdio-bus {
402          #address-cells = <1>;
403          #size-cells = <0>;
404
405          phy5: ethernet-phy@0 {
406            compatible = "ethernet-phy-id67c9.de0a";
407            phy-mode = "2500base-x";
408            reset-gpios = <&pio 6 1>;
409            reset-deassert-us = <20000>;
410            reg = <5>;
411          };
412
413          phy6: ethernet-phy@1 {
414            compatible = "ethernet-phy-id67c9.de0a";
415            phy-mode = "2500base-x";
416            reg = <6>;
417          };
418        };
419
420        mac0: mac@0 {
421          compatible = "mediatek,eth-mac";
422          phy-mode = "2500base-x";
423          phy-handle = <&phy5>;
424          reg = <0>;
425        };
426
427        mac1: mac@1 {
428          compatible = "mediatek,eth-mac";
429          phy-mode = "2500base-x";
430          phy-handle = <&phy6>;
431          reg = <1>;
432        };
433      };
434    };
435