xref: /linux/Documentation/devicetree/bindings/net/mediatek,net.yaml (revision 22ecfce11034e74504b3657c668db0d64d93c05e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7622-eth
23      - mediatek,mt7629-eth
24      - mediatek,mt7986-eth
25      - ralink,rt5350-eth
26
27  reg:
28    maxItems: 1
29
30  clocks: true
31  clock-names: true
32
33  interrupts:
34    minItems: 3
35    maxItems: 4
36
37  power-domains:
38    maxItems: 1
39
40  resets:
41    maxItems: 3
42
43  reset-names:
44    items:
45      - const: fe
46      - const: gmac
47      - const: ppe
48
49  mediatek,ethsys:
50    $ref: /schemas/types.yaml#/definitions/phandle
51    description:
52      Phandle to the syscon node that handles the port setup.
53
54  cci-control-port: true
55
56  mediatek,hifsys:
57    $ref: /schemas/types.yaml#/definitions/phandle
58    description:
59      Phandle to the mediatek hifsys controller used to provide various clocks
60      and reset to the system.
61
62  mediatek,sgmiisys:
63    $ref: /schemas/types.yaml#/definitions/phandle-array
64    minItems: 1
65    maxItems: 2
66    items:
67      maxItems: 1
68    description:
69      A list of phandle to the syscon node that handles the SGMII setup which is required for
70      those SoCs equipped with SGMII.
71
72  mediatek,wed:
73    $ref: /schemas/types.yaml#/definitions/phandle-array
74    minItems: 2
75    maxItems: 2
76    items:
77      maxItems: 1
78    description:
79      List of phandles to wireless ethernet dispatch nodes.
80
81  dma-coherent: true
82
83  mdio-bus:
84    $ref: mdio.yaml#
85    unevaluatedProperties: false
86
87  "#address-cells":
88    const: 1
89
90  "#size-cells":
91    const: 0
92
93allOf:
94  - $ref: "ethernet-controller.yaml#"
95  - if:
96      properties:
97        compatible:
98          contains:
99            enum:
100              - mediatek,mt2701-eth
101              - mediatek,mt7623-eth
102    then:
103      properties:
104        interrupts:
105          maxItems: 3
106
107        clocks:
108          minItems: 4
109          maxItems: 4
110
111        clock-names:
112          items:
113            - const: ethif
114            - const: esw
115            - const: gp1
116            - const: gp2
117
118        mediatek,pctl:
119          $ref: /schemas/types.yaml#/definitions/phandle
120          description:
121            Phandle to the syscon node that handles the ports slew rate and
122            driver current.
123
124        mediatek,wed: false
125
126  - if:
127      properties:
128        compatible:
129          contains:
130            const: mediatek,mt7622-eth
131    then:
132      properties:
133        interrupts:
134          maxItems: 3
135
136        clocks:
137          minItems: 11
138          maxItems: 11
139
140        clock-names:
141          items:
142            - const: ethif
143            - const: esw
144            - const: gp0
145            - const: gp1
146            - const: gp2
147            - const: sgmii_tx250m
148            - const: sgmii_rx250m
149            - const: sgmii_cdr_ref
150            - const: sgmii_cdr_fb
151            - const: sgmii_ck
152            - const: eth2pll
153
154        mediatek,sgmiisys:
155          minItems: 1
156          maxItems: 1
157
158        mediatek,pcie-mirror:
159          $ref: /schemas/types.yaml#/definitions/phandle
160          description:
161            Phandle to the mediatek pcie-mirror controller.
162
163  - if:
164      properties:
165        compatible:
166          contains:
167            const: mediatek,mt7629-eth
168    then:
169      properties:
170        interrupts:
171          maxItems: 3
172
173        clocks:
174          minItems: 17
175          maxItems: 17
176
177        clock-names:
178          items:
179            - const: ethif
180            - const: sgmiitop
181            - const: esw
182            - const: gp0
183            - const: gp1
184            - const: gp2
185            - const: fe
186            - const: sgmii_tx250m
187            - const: sgmii_rx250m
188            - const: sgmii_cdr_ref
189            - const: sgmii_cdr_fb
190            - const: sgmii2_tx250m
191            - const: sgmii2_rx250m
192            - const: sgmii2_cdr_ref
193            - const: sgmii2_cdr_fb
194            - const: sgmii_ck
195            - const: eth2pll
196
197        mediatek,infracfg:
198          $ref: /schemas/types.yaml#/definitions/phandle
199          description:
200            Phandle to the syscon node that handles the path from GMAC to
201            PHY variants.
202
203        mediatek,sgmiisys:
204          minItems: 2
205          maxItems: 2
206
207        mediatek,wed: false
208
209  - if:
210      properties:
211        compatible:
212          contains:
213            const: mediatek,mt7986-eth
214    then:
215      properties:
216        interrupts:
217          minItems: 4
218
219        clocks:
220          minItems: 15
221          maxItems: 15
222
223        clock-names:
224          items:
225            - const: fe
226            - const: gp2
227            - const: gp1
228            - const: wocpu1
229            - const: wocpu0
230            - const: sgmii_tx250m
231            - const: sgmii_rx250m
232            - const: sgmii_cdr_ref
233            - const: sgmii_cdr_fb
234            - const: sgmii2_tx250m
235            - const: sgmii2_rx250m
236            - const: sgmii2_cdr_ref
237            - const: sgmii2_cdr_fb
238            - const: netsys0
239            - const: netsys1
240
241        mediatek,sgmiisys:
242          minItems: 2
243          maxItems: 2
244
245        mediatek,wed-pcie:
246          $ref: /schemas/types.yaml#/definitions/phandle
247          description:
248            Phandle to the mediatek wed-pcie controller.
249
250patternProperties:
251  "^mac@[0-1]$":
252    type: object
253    additionalProperties: false
254    allOf:
255      - $ref: ethernet-controller.yaml#
256    description:
257      Ethernet MAC node
258    properties:
259      compatible:
260        const: mediatek,eth-mac
261
262      reg:
263        maxItems: 1
264
265      phy-handle: true
266
267      phy-mode: true
268
269    required:
270      - reg
271      - compatible
272      - phy-handle
273
274required:
275  - compatible
276  - reg
277  - interrupts
278  - clocks
279  - clock-names
280  - mediatek,ethsys
281
282unevaluatedProperties: false
283
284examples:
285  - |
286    #include <dt-bindings/interrupt-controller/arm-gic.h>
287    #include <dt-bindings/interrupt-controller/irq.h>
288    #include <dt-bindings/clock/mt7622-clk.h>
289    #include <dt-bindings/power/mt7622-power.h>
290
291    soc {
292      #address-cells = <2>;
293      #size-cells = <2>;
294
295      ethernet: ethernet@1b100000 {
296        compatible = "mediatek,mt7622-eth";
297        reg = <0 0x1b100000 0 0x20000>;
298        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
299                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
300                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
301        clocks = <&topckgen CLK_TOP_ETH_SEL>,
302                 <&ethsys CLK_ETH_ESW_EN>,
303                 <&ethsys CLK_ETH_GP0_EN>,
304                 <&ethsys CLK_ETH_GP1_EN>,
305                 <&ethsys CLK_ETH_GP2_EN>,
306                 <&sgmiisys CLK_SGMII_TX250M_EN>,
307                 <&sgmiisys CLK_SGMII_RX250M_EN>,
308                 <&sgmiisys CLK_SGMII_CDR_REF>,
309                 <&sgmiisys CLK_SGMII_CDR_FB>,
310                 <&topckgen CLK_TOP_SGMIIPLL>,
311                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
312        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
313                      "sgmii_tx250m", "sgmii_rx250m",
314                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
315                      "eth2pll";
316        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
317        mediatek,ethsys = <&ethsys>;
318        mediatek,sgmiisys = <&sgmiisys>;
319        cci-control-port = <&cci_control2>;
320        mediatek,pcie-mirror = <&pcie_mirror>;
321        mediatek,hifsys = <&hifsys>;
322        dma-coherent;
323
324        #address-cells = <1>;
325        #size-cells = <0>;
326
327        mdio0: mdio-bus {
328          #address-cells = <1>;
329          #size-cells = <0>;
330
331          phy0: ethernet-phy@0 {
332            reg = <0>;
333          };
334
335          phy1: ethernet-phy@1 {
336            reg = <1>;
337          };
338        };
339
340        gmac0: mac@0 {
341          compatible = "mediatek,eth-mac";
342          phy-mode = "rgmii";
343          phy-handle = <&phy0>;
344          reg = <0>;
345        };
346
347        gmac1: mac@1 {
348          compatible = "mediatek,eth-mac";
349          phy-mode = "rgmii";
350          phy-handle = <&phy1>;
351          reg = <1>;
352        };
353      };
354    };
355
356  - |
357    #include <dt-bindings/interrupt-controller/arm-gic.h>
358    #include <dt-bindings/interrupt-controller/irq.h>
359    #include <dt-bindings/clock/mt7622-clk.h>
360
361    soc {
362      #address-cells = <2>;
363      #size-cells = <2>;
364
365      eth: ethernet@15100000 {
366        #define CLK_ETH_FE_EN               0
367        #define CLK_ETH_WOCPU1_EN           3
368        #define CLK_ETH_WOCPU0_EN           4
369        #define CLK_TOP_NETSYS_SEL          43
370        #define CLK_TOP_NETSYS_500M_SEL     44
371        #define CLK_TOP_NETSYS_2X_SEL       46
372        #define CLK_TOP_SGM_325M_SEL        47
373        #define CLK_APMIXED_NET2PLL         1
374        #define CLK_APMIXED_SGMPLL          3
375
376        compatible = "mediatek,mt7986-eth";
377        reg = <0 0x15100000 0 0x80000>;
378        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
379                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
380                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
381                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
382        clocks = <&ethsys CLK_ETH_FE_EN>,
383                 <&ethsys CLK_ETH_GP2_EN>,
384                 <&ethsys CLK_ETH_GP1_EN>,
385                 <&ethsys CLK_ETH_WOCPU1_EN>,
386                 <&ethsys CLK_ETH_WOCPU0_EN>,
387                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
388                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
389                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
390                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
391                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
392                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
393                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
394                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
395                 <&topckgen CLK_TOP_NETSYS_SEL>,
396                 <&topckgen CLK_TOP_NETSYS_SEL>;
397        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
398                      "sgmii_tx250m", "sgmii_rx250m",
399                      "sgmii_cdr_ref", "sgmii_cdr_fb",
400                      "sgmii2_tx250m", "sgmii2_rx250m",
401                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
402                      "netsys0", "netsys1";
403        mediatek,ethsys = <&ethsys>;
404        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
405        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
406                          <&topckgen CLK_TOP_SGM_325M_SEL>;
407        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
408                                 <&apmixedsys CLK_APMIXED_SGMPLL>;
409
410        #address-cells = <1>;
411        #size-cells = <0>;
412
413        mdio: mdio-bus {
414          #address-cells = <1>;
415          #size-cells = <0>;
416
417          phy5: ethernet-phy@0 {
418            compatible = "ethernet-phy-id67c9.de0a";
419            phy-mode = "2500base-x";
420            reset-gpios = <&pio 6 1>;
421            reset-deassert-us = <20000>;
422            reg = <5>;
423          };
424
425          phy6: ethernet-phy@1 {
426            compatible = "ethernet-phy-id67c9.de0a";
427            phy-mode = "2500base-x";
428            reg = <6>;
429          };
430        };
431
432        mac0: mac@0 {
433          compatible = "mediatek,eth-mac";
434          phy-mode = "2500base-x";
435          phy-handle = <&phy5>;
436          reg = <0>;
437        };
438
439        mac1: mac@1 {
440          compatible = "mediatek,eth-mac";
441          phy-mode = "2500base-x";
442          phy-handle = <&phy6>;
443          reg = <1>;
444        };
445      };
446    };
447