1d524dac9SGrant Likely* MDIO IO device 2d524dac9SGrant Likely 3d524dac9SGrant LikelyThe MDIO is a bus to which the PHY devices are connected. For each 4d524dac9SGrant Likelydevice that exists on this bus, a child node should be created. See 5d524dac9SGrant Likelythe definition of the PHY node in booting-without-of.txt for an example 6d524dac9SGrant Likelyof how to define a PHY. 7d524dac9SGrant Likely 8d524dac9SGrant LikelyRequired properties: 9d524dac9SGrant Likely - reg : Offset and length of the register set for the device 10d524dac9SGrant Likely - compatible : Should define the compatible device type for the 11d524dac9SGrant Likely mdio. Currently, this is most likely to be "fsl,gianfar-mdio" 12d524dac9SGrant Likely 13d524dac9SGrant LikelyExample: 14d524dac9SGrant Likely 15d524dac9SGrant Likely mdio@24520 { 16d524dac9SGrant Likely reg = <24520 20>; 17d524dac9SGrant Likely compatible = "fsl,gianfar-mdio"; 18d524dac9SGrant Likely 19d524dac9SGrant Likely ethernet-phy@0 { 20d524dac9SGrant Likely ...... 21d524dac9SGrant Likely }; 22d524dac9SGrant Likely }; 23d524dac9SGrant Likely 24d524dac9SGrant Likely* TBI Internal MDIO bus 25d524dac9SGrant Likely 26d524dac9SGrant LikelyAs of this writing, every tsec is associated with an internal TBI PHY. 27d524dac9SGrant LikelyThis PHY is accessed through the local MDIO bus. These buses are defined 28d524dac9SGrant Likelysimilarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi". 29d524dac9SGrant LikelyThe TBI PHYs underneath them are similar to normal PHYs, but the reg property 30d524dac9SGrant Likelyis considered instructive, rather than descriptive. The reg property should 31d524dac9SGrant Likelybe chosen so it doesn't interfere with other PHYs on the bus. 32d524dac9SGrant Likely 33d524dac9SGrant Likely* Gianfar-compatible ethernet nodes 34d524dac9SGrant Likely 35d524dac9SGrant LikelyProperties: 36d524dac9SGrant Likely 37d524dac9SGrant Likely - device_type : Should be "network" 38d524dac9SGrant Likely - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC" 39d524dac9SGrant Likely - compatible : Should be "gianfar" 40d524dac9SGrant Likely - reg : Offset and length of the register set for the device 41d524dac9SGrant Likely - local-mac-address : List of bytes representing the ethernet address of 42d524dac9SGrant Likely this controller 43d524dac9SGrant Likely - interrupts : For FEC devices, the first interrupt is the device's 44d524dac9SGrant Likely interrupt. For TSEC and eTSEC devices, the first interrupt is 45d524dac9SGrant Likely transmit, the second is receive, and the third is error. 46d524dac9SGrant Likely - phy-handle : The phandle for the PHY connected to this ethernet 47d524dac9SGrant Likely controller. 48d524dac9SGrant Likely - fixed-link : <a b c d e> where a is emulated phy id - choose any, 49d524dac9SGrant Likely but unique to the all specified fixed-links, b is duplex - 0 half, 50d524dac9SGrant Likely 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no 51d524dac9SGrant Likely pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause. 52d524dac9SGrant Likely - phy-connection-type : a string naming the controller/PHY interface type, 53d524dac9SGrant Likely i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii", 54d524dac9SGrant Likely "tbi", or "rtbi". This property is only really needed if the connection 55d524dac9SGrant Likely is of type "rgmii-id", as all other connection types are detected by 56d524dac9SGrant Likely hardware. 57d524dac9SGrant Likely - fsl,magic-packet : If present, indicates that the hardware supports 58d524dac9SGrant Likely waking up via magic packet. 59d524dac9SGrant Likely - bd-stash : If present, indicates that the hardware supports stashing 60d524dac9SGrant Likely buffer descriptors in the L2. 61d524dac9SGrant Likely - rx-stash-len : Denotes the number of bytes of a received buffer to stash 62d524dac9SGrant Likely in the L2. 63d524dac9SGrant Likely - rx-stash-idx : Denotes the index of the first byte from the received 64d524dac9SGrant Likely buffer to stash in the L2. 65d524dac9SGrant Likely 66d524dac9SGrant LikelyExample: 67d524dac9SGrant Likely ethernet@24000 { 68d524dac9SGrant Likely device_type = "network"; 69d524dac9SGrant Likely model = "TSEC"; 70d524dac9SGrant Likely compatible = "gianfar"; 71d524dac9SGrant Likely reg = <0x24000 0x1000>; 72d524dac9SGrant Likely local-mac-address = [ 00 E0 0C 00 73 00 ]; 73d524dac9SGrant Likely interrupts = <29 2 30 2 34 2>; 74d524dac9SGrant Likely interrupt-parent = <&mpic>; 75d524dac9SGrant Likely phy-handle = <&phy0> 76d524dac9SGrant Likely }; 77*c78275f3SRichard Cochran 78*c78275f3SRichard Cochran* Gianfar PTP clock nodes 79*c78275f3SRichard Cochran 80*c78275f3SRichard CochranGeneral Properties: 81*c78275f3SRichard Cochran 82*c78275f3SRichard Cochran - compatible Should be "fsl,etsec-ptp" 83*c78275f3SRichard Cochran - reg Offset and length of the register set for the device 84*c78275f3SRichard Cochran - interrupts There should be at least two interrupts. Some devices 85*c78275f3SRichard Cochran have as many as four PTP related interrupts. 86*c78275f3SRichard Cochran 87*c78275f3SRichard CochranClock Properties: 88*c78275f3SRichard Cochran 89*c78275f3SRichard Cochran - fsl,tclk-period Timer reference clock period in nanoseconds. 90*c78275f3SRichard Cochran - fsl,tmr-prsc Prescaler, divides the output clock. 91*c78275f3SRichard Cochran - fsl,tmr-add Frequency compensation value. 92*c78275f3SRichard Cochran - fsl,tmr-fiper1 Fixed interval period pulse generator. 93*c78275f3SRichard Cochran - fsl,tmr-fiper2 Fixed interval period pulse generator. 94*c78275f3SRichard Cochran - fsl,max-adj Maximum frequency adjustment in parts per billion. 95*c78275f3SRichard Cochran 96*c78275f3SRichard Cochran These properties set the operational parameters for the PTP 97*c78275f3SRichard Cochran clock. You must choose these carefully for the clock to work right. 98*c78275f3SRichard Cochran Here is how to figure good values: 99*c78275f3SRichard Cochran 100*c78275f3SRichard Cochran TimerOsc = system clock MHz 101*c78275f3SRichard Cochran tclk_period = desired clock period nanoseconds 102*c78275f3SRichard Cochran NominalFreq = 1000 / tclk_period MHz 103*c78275f3SRichard Cochran FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0) 104*c78275f3SRichard Cochran tmr_add = ceil(2^32 / FreqDivRatio) 105*c78275f3SRichard Cochran OutputClock = NominalFreq / tmr_prsc MHz 106*c78275f3SRichard Cochran PulseWidth = 1 / OutputClock microseconds 107*c78275f3SRichard Cochran FiperFreq1 = desired frequency in Hz 108*c78275f3SRichard Cochran FiperDiv1 = 1000000 * OutputClock / FiperFreq1 109*c78275f3SRichard Cochran tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period 110*c78275f3SRichard Cochran max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1 111*c78275f3SRichard Cochran 112*c78275f3SRichard Cochran The calculation for tmr_fiper2 is the same as for tmr_fiper1. The 113*c78275f3SRichard Cochran driver expects that tmr_fiper1 will be correctly set to produce a 1 114*c78275f3SRichard Cochran Pulse Per Second (PPS) signal, since this will be offered to the PPS 115*c78275f3SRichard Cochran subsystem to synchronize the Linux clock. 116*c78275f3SRichard Cochran 117*c78275f3SRichard CochranExample: 118*c78275f3SRichard Cochran 119*c78275f3SRichard Cochran ptp_clock@24E00 { 120*c78275f3SRichard Cochran compatible = "fsl,etsec-ptp"; 121*c78275f3SRichard Cochran reg = <0x24E00 0xB0>; 122*c78275f3SRichard Cochran interrupts = <12 0x8 13 0x8>; 123*c78275f3SRichard Cochran interrupt-parent = < &ipic >; 124*c78275f3SRichard Cochran fsl,tclk-period = <10>; 125*c78275f3SRichard Cochran fsl,tmr-prsc = <100>; 126*c78275f3SRichard Cochran fsl,tmr-add = <0x999999A4>; 127*c78275f3SRichard Cochran fsl,tmr-fiper1 = <0x3B9AC9F6>; 128*c78275f3SRichard Cochran fsl,tmr-fiper2 = <0x00018696>; 129*c78275f3SRichard Cochran fsl,max-adj = <659999998>; 130*c78275f3SRichard Cochran }; 131