1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/fsl,fec.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Fast Ethernet Controller (FEC) 8 9maintainers: 10 - Shawn Guo <shawnguo@kernel.org> 11 - Wei Fang <wei.fang@nxp.com> 12 - NXP Linux Team <linux-imx@nxp.com> 13 14allOf: 15 - $ref: ethernet-controller.yaml# 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - fsl,imx25-fec 22 - fsl,imx27-fec 23 - fsl,imx28-fec 24 - fsl,imx6q-fec 25 - fsl,mvf600-fec 26 - fsl,s32v234-fec 27 - items: 28 - enum: 29 - fsl,imx53-fec 30 - fsl,imx6sl-fec 31 - const: fsl,imx25-fec 32 - items: 33 - enum: 34 - fsl,imx35-fec 35 - fsl,imx51-fec 36 - const: fsl,imx27-fec 37 - items: 38 - enum: 39 - fsl,imx6ul-fec 40 - fsl,imx6sx-fec 41 - const: fsl,imx6q-fec 42 - items: 43 - enum: 44 - fsl,imx7d-fec 45 - const: fsl,imx6sx-fec 46 - items: 47 - const: fsl,imx8mq-fec 48 - const: fsl,imx6sx-fec 49 - items: 50 - enum: 51 - fsl,imx8mm-fec 52 - fsl,imx8mn-fec 53 - fsl,imx8mp-fec 54 - const: fsl,imx8mq-fec 55 - const: fsl,imx6sx-fec 56 - items: 57 - const: fsl,imx8qm-fec 58 - const: fsl,imx6sx-fec 59 - items: 60 - enum: 61 - fsl,imx8qxp-fec 62 - const: fsl,imx8qm-fec 63 - const: fsl,imx6sx-fec 64 - items: 65 - enum: 66 - fsl,imx8ulp-fec 67 - const: fsl,imx6ul-fec 68 - const: fsl,imx6q-fec 69 70 reg: 71 maxItems: 1 72 73 interrupts: 74 minItems: 1 75 maxItems: 4 76 77 interrupt-names: 78 oneOf: 79 - items: 80 - const: int0 81 - items: 82 - const: int0 83 - const: pps 84 - items: 85 - const: int0 86 - const: int1 87 - const: int2 88 - items: 89 - const: int0 90 - const: int1 91 - const: int2 92 - const: pps 93 94 clocks: 95 minItems: 2 96 maxItems: 5 97 description: 98 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. 99 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. 100 The "ptp"(option), for IEEE1588 timer clock that requires the clock. 101 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like 102 RGMII TXC clock or RMII reference clock. It depends on board design, 103 the clock is required if RGMII TXC and RMII reference clock source from 104 SOC internal PLL. 105 The "enet_out"(option), output clock for external device, like supply clock 106 for PHY. The clock is required if PHY clock source from SOC. 107 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz. 108 The clock is required if SoC RGMII enable clock delay. 109 110 clock-names: 111 minItems: 2 112 maxItems: 5 113 items: 114 enum: 115 - ipg 116 - ahb 117 - ptp 118 - enet_clk_ref 119 - enet_out 120 - enet_2x_txclk 121 122 phy-mode: true 123 124 phy-handle: true 125 126 fixed-link: true 127 128 local-mac-address: true 129 130 mac-address: true 131 132 nvmem-cells: true 133 134 nvmem-cell-names: true 135 136 tx-internal-delay-ps: 137 enum: [0, 2000] 138 139 rx-internal-delay-ps: 140 enum: [0, 2000] 141 142 phy-supply: 143 description: 144 Regulator that powers the Ethernet PHY. 145 146 fsl,num-tx-queues: 147 $ref: /schemas/types.yaml#/definitions/uint32 148 description: 149 The property is valid for enet-avb IP, which supports hw multi queues. 150 Should specify the tx queue number, otherwise set tx queue number to 1. 151 enum: [1, 2, 3] 152 153 fsl,num-rx-queues: 154 $ref: /schemas/types.yaml#/definitions/uint32 155 description: 156 The property is valid for enet-avb IP, which supports hw multi queues. 157 Should specify the rx queue number, otherwise set rx queue number to 1. 158 enum: [1, 2, 3] 159 160 fsl,magic-packet: 161 $ref: /schemas/types.yaml#/definitions/flag 162 description: 163 If present, indicates that the hardware supports waking up via magic packet. 164 165 fsl,err006687-workaround-present: 166 $ref: /schemas/types.yaml#/definitions/flag 167 description: 168 If present indicates that the system has the hardware workaround for 169 ERR006687 applied and does not need a software workaround. 170 171 fsl,stop-mode: 172 $ref: /schemas/types.yaml#/definitions/phandle-array 173 items: 174 - items: 175 - description: phandle to general purpose register node 176 - description: the gpr register offset for ENET stop request 177 - description: the gpr bit offset for ENET stop request 178 description: 179 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. 180 181 mdio: 182 $ref: mdio.yaml# 183 unevaluatedProperties: false 184 description: 185 Specifies the mdio bus in the FEC, used as a container for phy nodes. 186 187 # Deprecated optional properties: 188 # To avoid these, create a phy node according to ethernet-phy.yaml in the same 189 # directory, and point the FEC's "phy-handle" property to it. Then use 190 # the phy's reset binding, again described by ethernet-phy.yaml. 191 192 phy-reset-gpios: 193 deprecated: true 194 description: 195 Should specify the gpio for phy reset. 196 197 phy-reset-duration: 198 $ref: /schemas/types.yaml#/definitions/uint32 199 deprecated: true 200 description: 201 Reset duration in milliseconds. Should present only if property 202 "phy-reset-gpios" is available. Missing the property will have the 203 duration be 1 millisecond. Numbers greater than 1000 are invalid 204 and 1 millisecond will be used instead. 205 206 phy-reset-active-high: 207 type: boolean 208 deprecated: true 209 description: 210 If present then the reset sequence using the GPIO specified in the 211 "phy-reset-gpios" property is reversed (H=reset state, L=operation state). 212 213 phy-reset-post-delay: 214 $ref: /schemas/types.yaml#/definitions/uint32 215 deprecated: true 216 description: 217 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay 218 milliseconds will be observed after the phy-reset-gpios has been toggled. 219 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. 220 Other delays are invalid. 221 222required: 223 - compatible 224 - reg 225 - interrupts 226 227# FIXME: We had better set additionalProperties to false to avoid invalid or at 228# least undocumented properties. However, PHY may have a deprecated option to 229# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find 230# these boards which is based on i.MX6QDL. 231unevaluatedProperties: false 232 233examples: 234 - | 235 ethernet@83fec000 { 236 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 237 reg = <0x83fec000 0x4000>; 238 interrupts = <87>; 239 phy-mode = "mii"; 240 phy-reset-gpios = <&gpio2 14 0>; 241 phy-supply = <®_fec_supply>; 242 }; 243 244 ethernet@83fed000 { 245 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 246 reg = <0x83fed000 0x4000>; 247 interrupts = <87>; 248 phy-mode = "mii"; 249 phy-reset-gpios = <&gpio2 14 0>; 250 phy-supply = <®_fec_supply>; 251 phy-handle = <ðphy0>; 252 253 mdio { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 257 ethphy0: ethernet-phy@0 { 258 compatible = "ethernet-phy-ieee802.3-c22"; 259 reg = <0>; 260 }; 261 }; 262 }; 263