1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Ethernet PHY Common Properties 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 13 14# The dt-schema tools will generate a select statement first by using 15# the compatible, and second by using the node name if any. In our 16# case, the node name is the one we want to match on, while the 17# compatible is optional. 18select: 19 properties: 20 $nodename: 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 22 23 required: 24 - $nodename 25 26properties: 27 $nodename: 28 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 29 30 compatible: 31 oneOf: 32 - const: ethernet-phy-ieee802.3-c22 33 description: PHYs that implement IEEE802.3 clause 22 34 - const: ethernet-phy-ieee802.3-c45 35 description: PHYs that implement IEEE802.3 clause 45 36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 37 description: 38 PHYs contain identification registers. These will be read to 39 identify the PHY. If the PHY reports an incorrect ID, or the 40 PHY requires a specific initialization sequence (like a 41 particular order of clocks, resets, power supplies), in 42 order to be able to read the ID registers, then the 43 compatible list must contain an entry with the correct PHY 44 ID in the above form. 45 The first group of digits is the 16 bit Phy Identifier 1 46 register, this is the chip vendor OUI bits 3:18. The 47 second group of digits is the Phy Identifier 2 register, 48 this is the chip vendor OUI bits 19:24, followed by 10 49 bits of a vendor specific ID. 50 - items: 51 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 52 - const: ethernet-phy-ieee802.3-c22 53 - items: 54 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 55 - const: ethernet-phy-ieee802.3-c45 56 57 reg: 58 minimum: 0 59 maximum: 31 60 description: 61 The ID number for the PHY. 62 63 interrupts: 64 maxItems: 1 65 66 max-speed: 67 enum: 68 - 10 69 - 100 70 - 1000 71 - 2500 72 - 5000 73 - 10000 74 - 20000 75 - 25000 76 - 40000 77 - 50000 78 - 56000 79 - 100000 80 - 200000 81 description: 82 Maximum PHY supported speed in Mbits / seconds. 83 84 phy-10base-t1l-2.4vpp: 85 description: | 86 tristate, request/disable 2.4 Vpp operating mode. The values are: 87 0: Disable 2.4 Vpp operating mode. 88 1: Request 2.4 Vpp operating mode from link partner. 89 Absence of this property will leave configuration to default values. 90 $ref: /schemas/types.yaml#/definitions/uint32 91 enum: [0, 1] 92 93 broken-turn-around: 94 $ref: /schemas/types.yaml#/definitions/flag 95 description: 96 If set, indicates the PHY device does not correctly release 97 the turn around line low at end of the control phase of the 98 MDIO transaction. 99 100 brr-mode: 101 $ref: /schemas/types.yaml#/definitions/flag 102 description: 103 If set, indicates the network cable interface is an alternative one as 104 defined in the BroadR-Reach link mode specification under 1BR-100 and 105 1BR-10 names. The PHY must be configured to operate in BroadR-Reach mode 106 by software. 107 108 clocks: 109 minItems: 1 110 maxItems: 2 111 description: 112 External clock connected to the PHY or RX and TX clocks that the PHY 113 requires to enable explicitly. If not specified it is assumed 114 that the PHY uses a fixed crystal or an internal oscillator or that the 115 RX/TX clocks are hardware enabled by default. 116 117 enet-phy-lane-swap: 118 $ref: /schemas/types.yaml#/definitions/flag 119 description: 120 If set, indicates the PHY will swap the TX/RX lanes to 121 compensate for the board being designed with the lanes 122 swapped. 123 124 enet-phy-lane-no-swap: 125 $ref: /schemas/types.yaml#/definitions/flag 126 description: 127 If set, indicates that PHY will disable swap of the 128 TX/RX lanes. This property allows the PHY to work correctly after 129 e.g. wrong bootstrap configuration caused by issues in PCB 130 layout design. 131 132 enet-phy-pair-order: 133 $ref: /schemas/types.yaml#/definitions/uint32 134 enum: [0, 1] 135 description: 136 For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA). 137 138 enet-phy-pair-polarity: 139 $ref: /schemas/types.yaml#/definitions/uint32 140 maximum: 0xf 141 description: 142 A bitmap to describe pair polarity swap. Bit 0 to swap polarity of pair A, 143 bit 1 to swap polarity of pair B, bit 2 to swap polarity of pair C and bit 144 3 to swap polarity of pair D. 145 146 eee-broken-100tx: 147 $ref: /schemas/types.yaml#/definitions/flag 148 description: 149 Mark the corresponding energy efficient ethernet mode as 150 broken and request the ethernet to stop advertising it. 151 152 eee-broken-1000t: 153 $ref: /schemas/types.yaml#/definitions/flag 154 description: 155 Mark the corresponding energy efficient ethernet mode as 156 broken and request the ethernet to stop advertising it. 157 158 eee-broken-10gt: 159 $ref: /schemas/types.yaml#/definitions/flag 160 description: 161 Mark the corresponding energy efficient ethernet mode as 162 broken and request the ethernet to stop advertising it. 163 164 eee-broken-1000kx: 165 $ref: /schemas/types.yaml#/definitions/flag 166 description: 167 Mark the corresponding energy efficient ethernet mode as 168 broken and request the ethernet to stop advertising it. 169 170 eee-broken-10gkx4: 171 $ref: /schemas/types.yaml#/definitions/flag 172 description: 173 Mark the corresponding energy efficient ethernet mode as 174 broken and request the ethernet to stop advertising it. 175 176 eee-broken-10gkr: 177 $ref: /schemas/types.yaml#/definitions/flag 178 description: 179 Mark the corresponding energy efficient ethernet mode as 180 broken and request the ethernet to stop advertising it. 181 182 timing-role: 183 $ref: /schemas/types.yaml#/definitions/string 184 enum: 185 - forced-master 186 - forced-slave 187 - preferred-master 188 - preferred-slave 189 description: | 190 Specifies the timing role of the PHY in the network link. This property is 191 required for setups where the role must be explicitly assigned via the 192 device tree due to limitations in hardware strapping or incorrect strap 193 configurations. 194 It is applicable to Single Pair Ethernet (1000/100/10Base-T1) and other 195 PHY types, including 1000Base-T, where it controls whether the PHY should 196 be a master (clock source) or a slave (clock receiver). 197 198 - 'forced-master': The PHY is forced to operate as a master. 199 - 'forced-slave': The PHY is forced to operate as a slave. 200 - 'preferred-master': Prefer the PHY to be master but allow negotiation. 201 - 'preferred-slave': Prefer the PHY to be slave but allow negotiation. 202 203 pses: 204 $ref: /schemas/types.yaml#/definitions/phandle-array 205 maxItems: 1 206 description: 207 Specifies a reference to a node representing a Power Sourcing Equipment. 208 209 phy-is-integrated: 210 $ref: /schemas/types.yaml#/definitions/flag 211 description: 212 If set, indicates that the PHY is integrated into the same 213 physical package as the Ethernet MAC. If needed, muxers 214 should be configured to ensure the integrated PHY is 215 used. The absence of this property indicates the muxers 216 should be configured so that the external PHY is used. 217 218 resets: 219 maxItems: 1 220 221 reset-names: 222 const: phy 223 224 reset-gpios: 225 maxItems: 1 226 description: 227 The GPIO phandle and specifier for the PHY reset signal. 228 229 reset-assert-us: 230 description: 231 Delay after the reset was asserted in microseconds. If this 232 property is missing the delay will be skipped. 233 234 reset-deassert-us: 235 description: 236 Delay after the reset was deasserted in microseconds. If 237 this property is missing the delay will be skipped. 238 239 sfp: 240 $ref: /schemas/types.yaml#/definitions/phandle 241 description: 242 Specifies a reference to a node representing a SFP cage. 243 244 rx-internal-delay-ps: 245 description: | 246 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for 247 PHY's that have configurable RX internal delays. If this property is 248 present then the PHY applies the RX delay. 249 250 tx-internal-delay-ps: 251 description: | 252 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for 253 PHY's that have configurable TX internal delays. If this property is 254 present then the PHY applies the TX delay. 255 256 tx-amplitude-100base-tx-percent: 257 description: 258 Transmit amplitude gain applied for 100BASE-TX. 100% matches 2V 259 peak-to-peak specified in ANSI X3.263. When omitted, the PHYs default 260 will be left as is. 261 262 mac-termination-ohms: 263 maximum: 200 264 description: 265 The xMII signals need series termination on the driver side to match both 266 the output driver impedance and the line characteristic impedance, to 267 prevent reflections and EMI problems. Select a resistance value which is 268 supported by the builtin resistors of the PHY, otherwise the resistors may 269 have to be placed on board. When omitted, the PHYs default will be left as 270 is. 271 272 leds: 273 type: object 274 275 properties: 276 '#address-cells': 277 const: 1 278 279 '#size-cells': 280 const: 0 281 282 patternProperties: 283 '^led@[a-f0-9]+$': 284 $ref: /schemas/leds/common.yaml# 285 286 properties: 287 reg: 288 maxItems: 1 289 description: 290 This defines the LED index in the PHY or the MAC. It's really 291 driver dependent and required for ports that define multiple 292 LED for the same port. 293 294 required: 295 - reg 296 297 unevaluatedProperties: false 298 299 additionalProperties: false 300 301 mdi: 302 type: object 303 304 patternProperties: 305 '^connector-[0-9]+$': 306 $ref: /schemas/net/ethernet-connector.yaml# 307 308 unevaluatedProperties: false 309 310 additionalProperties: false 311 312required: 313 - reg 314 315additionalProperties: true 316 317examples: 318 - | 319 #include <dt-bindings/leds/common.h> 320 321 ethernet { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 ethernet-phy@0 { 326 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45"; 327 interrupt-parent = <&PIC>; 328 interrupts = <35 1>; 329 reg = <0>; 330 331 resets = <&rst 8>; 332 reset-names = "phy"; 333 reset-gpios = <&gpio1 4 1>; 334 reset-assert-us = <1000>; 335 reset-deassert-us = <2000>; 336 337 leds { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 341 led@0 { 342 reg = <0>; 343 color = <LED_COLOR_ID_WHITE>; 344 function = LED_FUNCTION_LAN; 345 default-state = "keep"; 346 }; 347 }; 348 /* Fast Ethernet port, with only 2 pairs wired */ 349 mdi { 350 connector-0 { 351 pairs = <2>; 352 media = "BaseT"; 353 }; 354 }; 355 }; 356 }; 357