1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Ethernet PHY Common Properties 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 13 14# The dt-schema tools will generate a select statement first by using 15# the compatible, and second by using the node name if any. In our 16# case, the node name is the one we want to match on, while the 17# compatible is optional. 18select: 19 properties: 20 $nodename: 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 22 23 required: 24 - $nodename 25 26properties: 27 $nodename: 28 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 29 30 compatible: 31 oneOf: 32 - const: ethernet-phy-ieee802.3-c22 33 description: PHYs that implement IEEE802.3 clause 22 34 - const: ethernet-phy-ieee802.3-c45 35 description: PHYs that implement IEEE802.3 clause 45 36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 37 description: 38 PHYs contain identification registers. These will be read to 39 identify the PHY. If the PHY reports an incorrect ID, or the 40 PHY requires a specific initialization sequence (like a 41 particular order of clocks, resets, power supplies), in 42 order to be able to read the ID registers, then the 43 compatible list must contain an entry with the correct PHY 44 ID in the above form. 45 The first group of digits is the 16 bit Phy Identifier 1 46 register, this is the chip vendor OUI bits 3:18. The 47 second group of digits is the Phy Identifier 2 register, 48 this is the chip vendor OUI bits 19:24, followed by 10 49 bits of a vendor specific ID. 50 - items: 51 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 52 - const: ethernet-phy-ieee802.3-c22 53 - items: 54 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 55 - const: ethernet-phy-ieee802.3-c45 56 57 reg: 58 minimum: 0 59 maximum: 31 60 description: 61 The ID number for the PHY. 62 63 interrupts: 64 maxItems: 1 65 66 max-speed: 67 enum: 68 - 10 69 - 100 70 - 1000 71 - 2500 72 - 5000 73 - 10000 74 - 20000 75 - 25000 76 - 40000 77 - 50000 78 - 56000 79 - 100000 80 - 200000 81 description: 82 Maximum PHY supported speed in Mbits / seconds. 83 84 phy-10base-t1l-2.4vpp: 85 description: | 86 tristate, request/disable 2.4 Vpp operating mode. The values are: 87 0: Disable 2.4 Vpp operating mode. 88 1: Request 2.4 Vpp operating mode from link partner. 89 Absence of this property will leave configuration to default values. 90 $ref: /schemas/types.yaml#/definitions/uint32 91 enum: [0, 1] 92 93 broken-turn-around: 94 $ref: /schemas/types.yaml#/definitions/flag 95 description: 96 If set, indicates the PHY device does not correctly release 97 the turn around line low at end of the control phase of the 98 MDIO transaction. 99 100 brr-mode: 101 $ref: /schemas/types.yaml#/definitions/flag 102 description: 103 If set, indicates the network cable interface is an alternative one as 104 defined in the BroadR-Reach link mode specification under 1BR-100 and 105 1BR-10 names. The PHY must be configured to operate in BroadR-Reach mode 106 by software. 107 108 clocks: 109 maxItems: 1 110 description: 111 External clock connected to the PHY. If not specified it is assumed 112 that the PHY uses a fixed crystal or an internal oscillator. 113 114 enet-phy-lane-swap: 115 $ref: /schemas/types.yaml#/definitions/flag 116 description: 117 If set, indicates the PHY will swap the TX/RX lanes to 118 compensate for the board being designed with the lanes 119 swapped. 120 121 enet-phy-lane-no-swap: 122 $ref: /schemas/types.yaml#/definitions/flag 123 description: 124 If set, indicates that PHY will disable swap of the 125 TX/RX lanes. This property allows the PHY to work correctly after 126 e.g. wrong bootstrap configuration caused by issues in PCB 127 layout design. 128 129 eee-broken-100tx: 130 $ref: /schemas/types.yaml#/definitions/flag 131 description: 132 Mark the corresponding energy efficient ethernet mode as 133 broken and request the ethernet to stop advertising it. 134 135 eee-broken-1000t: 136 $ref: /schemas/types.yaml#/definitions/flag 137 description: 138 Mark the corresponding energy efficient ethernet mode as 139 broken and request the ethernet to stop advertising it. 140 141 eee-broken-10gt: 142 $ref: /schemas/types.yaml#/definitions/flag 143 description: 144 Mark the corresponding energy efficient ethernet mode as 145 broken and request the ethernet to stop advertising it. 146 147 eee-broken-1000kx: 148 $ref: /schemas/types.yaml#/definitions/flag 149 description: 150 Mark the corresponding energy efficient ethernet mode as 151 broken and request the ethernet to stop advertising it. 152 153 eee-broken-10gkx4: 154 $ref: /schemas/types.yaml#/definitions/flag 155 description: 156 Mark the corresponding energy efficient ethernet mode as 157 broken and request the ethernet to stop advertising it. 158 159 eee-broken-10gkr: 160 $ref: /schemas/types.yaml#/definitions/flag 161 description: 162 Mark the corresponding energy efficient ethernet mode as 163 broken and request the ethernet to stop advertising it. 164 165 timing-role: 166 $ref: /schemas/types.yaml#/definitions/string 167 enum: 168 - forced-master 169 - forced-slave 170 - preferred-master 171 - preferred-slave 172 description: | 173 Specifies the timing role of the PHY in the network link. This property is 174 required for setups where the role must be explicitly assigned via the 175 device tree due to limitations in hardware strapping or incorrect strap 176 configurations. 177 It is applicable to Single Pair Ethernet (1000/100/10Base-T1) and other 178 PHY types, including 1000Base-T, where it controls whether the PHY should 179 be a master (clock source) or a slave (clock receiver). 180 181 - 'forced-master': The PHY is forced to operate as a master. 182 - 'forced-slave': The PHY is forced to operate as a slave. 183 - 'preferred-master': Prefer the PHY to be master but allow negotiation. 184 - 'preferred-slave': Prefer the PHY to be slave but allow negotiation. 185 186 pses: 187 $ref: /schemas/types.yaml#/definitions/phandle-array 188 maxItems: 1 189 description: 190 Specifies a reference to a node representing a Power Sourcing Equipment. 191 192 phy-is-integrated: 193 $ref: /schemas/types.yaml#/definitions/flag 194 description: 195 If set, indicates that the PHY is integrated into the same 196 physical package as the Ethernet MAC. If needed, muxers 197 should be configured to ensure the integrated PHY is 198 used. The absence of this property indicates the muxers 199 should be configured so that the external PHY is used. 200 201 resets: 202 maxItems: 1 203 204 reset-names: 205 const: phy 206 207 reset-gpios: 208 maxItems: 1 209 description: 210 The GPIO phandle and specifier for the PHY reset signal. 211 212 reset-assert-us: 213 description: 214 Delay after the reset was asserted in microseconds. If this 215 property is missing the delay will be skipped. 216 217 reset-deassert-us: 218 description: 219 Delay after the reset was deasserted in microseconds. If 220 this property is missing the delay will be skipped. 221 222 sfp: 223 $ref: /schemas/types.yaml#/definitions/phandle 224 description: 225 Specifies a reference to a node representing a SFP cage. 226 227 rx-internal-delay-ps: 228 description: | 229 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for 230 PHY's that have configurable RX internal delays. If this property is 231 present then the PHY applies the RX delay. 232 233 tx-internal-delay-ps: 234 description: | 235 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for 236 PHY's that have configurable TX internal delays. If this property is 237 present then the PHY applies the TX delay. 238 239 tx-amplitude-100base-tx-percent: 240 description: 241 Transmit amplitude gain applied for 100BASE-TX. 100% matches 2V 242 peak-to-peak specified in ANSI X3.263. When omitted, the PHYs default 243 will be left as is. 244 245 mac-termination-ohms: 246 maximum: 200 247 description: 248 The xMII signals need series termination on the driver side to match both 249 the output driver impedance and the line characteristic impedance, to 250 prevent reflections and EMI problems. Select a resistance value which is 251 supported by the builtin resistors of the PHY, otherwise the resistors may 252 have to be placed on board. When omitted, the PHYs default will be left as 253 is. 254 255 leds: 256 type: object 257 258 properties: 259 '#address-cells': 260 const: 1 261 262 '#size-cells': 263 const: 0 264 265 patternProperties: 266 '^led@[a-f0-9]+$': 267 $ref: /schemas/leds/common.yaml# 268 269 properties: 270 reg: 271 maxItems: 1 272 description: 273 This defines the LED index in the PHY or the MAC. It's really 274 driver dependent and required for ports that define multiple 275 LED for the same port. 276 277 required: 278 - reg 279 280 unevaluatedProperties: false 281 282 additionalProperties: false 283 284required: 285 - reg 286 287additionalProperties: true 288 289examples: 290 - | 291 #include <dt-bindings/leds/common.h> 292 293 ethernet { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 ethernet-phy@0 { 298 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45"; 299 interrupt-parent = <&PIC>; 300 interrupts = <35 1>; 301 reg = <0>; 302 303 resets = <&rst 8>; 304 reset-names = "phy"; 305 reset-gpios = <&gpio1 4 1>; 306 reset-assert-us = <1000>; 307 reset-deassert-us = <2000>; 308 309 leds { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 313 led@0 { 314 reg = <0>; 315 color = <LED_COLOR_ID_WHITE>; 316 function = LED_FUNCTION_LAN; 317 default-state = "keep"; 318 }; 319 }; 320 }; 321 }; 322