1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Ethernet PHY Common Properties 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 13 14# The dt-schema tools will generate a select statement first by using 15# the compatible, and second by using the node name if any. In our 16# case, the node name is the one we want to match on, while the 17# compatible is optional. 18select: 19 properties: 20 $nodename: 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 22 23 required: 24 - $nodename 25 26properties: 27 $nodename: 28 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 29 30 compatible: 31 oneOf: 32 - const: ethernet-phy-ieee802.3-c22 33 description: PHYs that implement IEEE802.3 clause 22 34 - const: ethernet-phy-ieee802.3-c45 35 description: PHYs that implement IEEE802.3 clause 45 36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 37 description: 38 PHYs contain identification registers. These will be read to 39 identify the PHY. If the PHY reports an incorrect ID, or the 40 PHY requires a specific initialization sequence (like a 41 particular order of clocks, resets, power supplies), in 42 order to be able to read the ID registers, then the 43 compatible list must contain an entry with the correct PHY 44 ID in the above form. 45 The first group of digits is the 16 bit Phy Identifier 1 46 register, this is the chip vendor OUI bits 3:18. The 47 second group of digits is the Phy Identifier 2 register, 48 this is the chip vendor OUI bits 19:24, followed by 10 49 bits of a vendor specific ID. 50 - items: 51 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 52 - const: ethernet-phy-ieee802.3-c22 53 - items: 54 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 55 - const: ethernet-phy-ieee802.3-c45 56 57 reg: 58 minimum: 0 59 maximum: 31 60 description: 61 The ID number for the PHY. 62 63 interrupts: 64 maxItems: 1 65 66 max-speed: 67 enum: 68 - 10 69 - 100 70 - 1000 71 - 2500 72 - 5000 73 - 10000 74 - 20000 75 - 25000 76 - 40000 77 - 50000 78 - 56000 79 - 100000 80 - 200000 81 description: 82 Maximum PHY supported speed in Mbits / seconds. 83 84 phy-10base-t1l-2.4vpp: 85 description: | 86 tristate, request/disable 2.4 Vpp operating mode. The values are: 87 0: Disable 2.4 Vpp operating mode. 88 1: Request 2.4 Vpp operating mode from link partner. 89 Absence of this property will leave configuration to default values. 90 $ref: /schemas/types.yaml#/definitions/uint32 91 enum: [0, 1] 92 93 broken-turn-around: 94 $ref: /schemas/types.yaml#/definitions/flag 95 description: 96 If set, indicates the PHY device does not correctly release 97 the turn around line low at end of the control phase of the 98 MDIO transaction. 99 100 brr-mode: 101 $ref: /schemas/types.yaml#/definitions/flag 102 description: 103 If set, indicates the network cable interface is an alternative one as 104 defined in the BroadR-Reach link mode specification under 1BR-100 and 105 1BR-10 names. The PHY must be configured to operate in BroadR-Reach mode 106 by software. 107 108 clocks: 109 maxItems: 1 110 description: 111 External clock connected to the PHY. If not specified it is assumed 112 that the PHY uses a fixed crystal or an internal oscillator. 113 114 enet-phy-lane-swap: 115 $ref: /schemas/types.yaml#/definitions/flag 116 description: 117 If set, indicates the PHY will swap the TX/RX lanes to 118 compensate for the board being designed with the lanes 119 swapped. 120 121 enet-phy-lane-no-swap: 122 $ref: /schemas/types.yaml#/definitions/flag 123 description: 124 If set, indicates that PHY will disable swap of the 125 TX/RX lanes. This property allows the PHY to work correctly after 126 e.g. wrong bootstrap configuration caused by issues in PCB 127 layout design. 128 129 enet-phy-pair-order: 130 $ref: /schemas/types.yaml#/definitions/uint32 131 enum: [0, 1] 132 description: 133 For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA). 134 135 enet-phy-pair-polarity: 136 $ref: /schemas/types.yaml#/definitions/uint32 137 maximum: 0xf 138 description: 139 A bitmap to describe pair polarity swap. Bit 0 to swap polarity of pair A, 140 bit 1 to swap polarity of pair B, bit 2 to swap polarity of pair C and bit 141 3 to swap polarity of pair D. 142 143 eee-broken-100tx: 144 $ref: /schemas/types.yaml#/definitions/flag 145 description: 146 Mark the corresponding energy efficient ethernet mode as 147 broken and request the ethernet to stop advertising it. 148 149 eee-broken-1000t: 150 $ref: /schemas/types.yaml#/definitions/flag 151 description: 152 Mark the corresponding energy efficient ethernet mode as 153 broken and request the ethernet to stop advertising it. 154 155 eee-broken-10gt: 156 $ref: /schemas/types.yaml#/definitions/flag 157 description: 158 Mark the corresponding energy efficient ethernet mode as 159 broken and request the ethernet to stop advertising it. 160 161 eee-broken-1000kx: 162 $ref: /schemas/types.yaml#/definitions/flag 163 description: 164 Mark the corresponding energy efficient ethernet mode as 165 broken and request the ethernet to stop advertising it. 166 167 eee-broken-10gkx4: 168 $ref: /schemas/types.yaml#/definitions/flag 169 description: 170 Mark the corresponding energy efficient ethernet mode as 171 broken and request the ethernet to stop advertising it. 172 173 eee-broken-10gkr: 174 $ref: /schemas/types.yaml#/definitions/flag 175 description: 176 Mark the corresponding energy efficient ethernet mode as 177 broken and request the ethernet to stop advertising it. 178 179 timing-role: 180 $ref: /schemas/types.yaml#/definitions/string 181 enum: 182 - forced-master 183 - forced-slave 184 - preferred-master 185 - preferred-slave 186 description: | 187 Specifies the timing role of the PHY in the network link. This property is 188 required for setups where the role must be explicitly assigned via the 189 device tree due to limitations in hardware strapping or incorrect strap 190 configurations. 191 It is applicable to Single Pair Ethernet (1000/100/10Base-T1) and other 192 PHY types, including 1000Base-T, where it controls whether the PHY should 193 be a master (clock source) or a slave (clock receiver). 194 195 - 'forced-master': The PHY is forced to operate as a master. 196 - 'forced-slave': The PHY is forced to operate as a slave. 197 - 'preferred-master': Prefer the PHY to be master but allow negotiation. 198 - 'preferred-slave': Prefer the PHY to be slave but allow negotiation. 199 200 pses: 201 $ref: /schemas/types.yaml#/definitions/phandle-array 202 maxItems: 1 203 description: 204 Specifies a reference to a node representing a Power Sourcing Equipment. 205 206 phy-is-integrated: 207 $ref: /schemas/types.yaml#/definitions/flag 208 description: 209 If set, indicates that the PHY is integrated into the same 210 physical package as the Ethernet MAC. If needed, muxers 211 should be configured to ensure the integrated PHY is 212 used. The absence of this property indicates the muxers 213 should be configured so that the external PHY is used. 214 215 resets: 216 maxItems: 1 217 218 reset-names: 219 const: phy 220 221 reset-gpios: 222 maxItems: 1 223 description: 224 The GPIO phandle and specifier for the PHY reset signal. 225 226 reset-assert-us: 227 description: 228 Delay after the reset was asserted in microseconds. If this 229 property is missing the delay will be skipped. 230 231 reset-deassert-us: 232 description: 233 Delay after the reset was deasserted in microseconds. If 234 this property is missing the delay will be skipped. 235 236 sfp: 237 $ref: /schemas/types.yaml#/definitions/phandle 238 description: 239 Specifies a reference to a node representing a SFP cage. 240 241 rx-internal-delay-ps: 242 description: | 243 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for 244 PHY's that have configurable RX internal delays. If this property is 245 present then the PHY applies the RX delay. 246 247 tx-internal-delay-ps: 248 description: | 249 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for 250 PHY's that have configurable TX internal delays. If this property is 251 present then the PHY applies the TX delay. 252 253 tx-amplitude-100base-tx-percent: 254 description: 255 Transmit amplitude gain applied for 100BASE-TX. 100% matches 2V 256 peak-to-peak specified in ANSI X3.263. When omitted, the PHYs default 257 will be left as is. 258 259 mac-termination-ohms: 260 maximum: 200 261 description: 262 The xMII signals need series termination on the driver side to match both 263 the output driver impedance and the line characteristic impedance, to 264 prevent reflections and EMI problems. Select a resistance value which is 265 supported by the builtin resistors of the PHY, otherwise the resistors may 266 have to be placed on board. When omitted, the PHYs default will be left as 267 is. 268 269 leds: 270 type: object 271 272 properties: 273 '#address-cells': 274 const: 1 275 276 '#size-cells': 277 const: 0 278 279 patternProperties: 280 '^led@[a-f0-9]+$': 281 $ref: /schemas/leds/common.yaml# 282 283 properties: 284 reg: 285 maxItems: 1 286 description: 287 This defines the LED index in the PHY or the MAC. It's really 288 driver dependent and required for ports that define multiple 289 LED for the same port. 290 291 required: 292 - reg 293 294 unevaluatedProperties: false 295 296 additionalProperties: false 297 298 mdi: 299 type: object 300 301 patternProperties: 302 '^connector-[0-9]+$': 303 $ref: /schemas/net/ethernet-connector.yaml# 304 305 unevaluatedProperties: false 306 307 additionalProperties: false 308 309required: 310 - reg 311 312additionalProperties: true 313 314examples: 315 - | 316 #include <dt-bindings/leds/common.h> 317 318 ethernet { 319 #address-cells = <1>; 320 #size-cells = <0>; 321 322 ethernet-phy@0 { 323 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45"; 324 interrupt-parent = <&PIC>; 325 interrupts = <35 1>; 326 reg = <0>; 327 328 resets = <&rst 8>; 329 reset-names = "phy"; 330 reset-gpios = <&gpio1 4 1>; 331 reset-assert-us = <1000>; 332 reset-deassert-us = <2000>; 333 334 leds { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 338 led@0 { 339 reg = <0>; 340 color = <LED_COLOR_ID_WHITE>; 341 function = LED_FUNCTION_LAN; 342 default-state = "keep"; 343 }; 344 }; 345 /* Fast Ethernet port, with only 2 pairs wired */ 346 mdi { 347 connector-0 { 348 pairs = <2>; 349 media = "BaseT"; 350 }; 351 }; 352 }; 353 }; 354