1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Ethernet PHY Generic Binding 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 13 14# The dt-schema tools will generate a select statement first by using 15# the compatible, and second by using the node name if any. In our 16# case, the node name is the one we want to match on, while the 17# compatible is optional. 18select: 19 properties: 20 $nodename: 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 22 23 required: 24 - $nodename 25 26properties: 27 $nodename: 28 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 29 30 compatible: 31 oneOf: 32 - const: ethernet-phy-ieee802.3-c22 33 description: PHYs that implement IEEE802.3 clause 22 34 - const: ethernet-phy-ieee802.3-c45 35 description: PHYs that implement IEEE802.3 clause 45 36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 37 description: 38 If the PHY reports an incorrect ID (or none at all) then the 39 compatible list may contain an entry with the correct PHY ID 40 in the above form. 41 The first group of digits is the 16 bit Phy Identifier 1 42 register, this is the chip vendor OUI bits 3:18. The 43 second group of digits is the Phy Identifier 2 register, 44 this is the chip vendor OUI bits 19:24, followed by 10 45 bits of a vendor specific ID. 46 - items: 47 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 48 - const: ethernet-phy-ieee802.3-c22 49 - items: 50 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 51 - const: ethernet-phy-ieee802.3-c45 52 53 reg: 54 minimum: 0 55 maximum: 31 56 description: 57 The ID number for the PHY. 58 59 interrupts: 60 maxItems: 1 61 62 max-speed: 63 enum: 64 - 10 65 - 100 66 - 1000 67 - 2500 68 - 5000 69 - 10000 70 - 20000 71 - 25000 72 - 40000 73 - 50000 74 - 56000 75 - 100000 76 - 200000 77 description: 78 Maximum PHY supported speed in Mbits / seconds. 79 80 broken-turn-around: 81 $ref: /schemas/types.yaml#/definitions/flag 82 description: 83 If set, indicates the PHY device does not correctly release 84 the turn around line low at end of the control phase of the 85 MDIO transaction. 86 87 enet-phy-lane-swap: 88 $ref: /schemas/types.yaml#/definitions/flag 89 description: 90 If set, indicates the PHY will swap the TX/RX lanes to 91 compensate for the board being designed with the lanes 92 swapped. 93 94 enet-phy-lane-no-swap: 95 $ref: /schemas/types.yaml#/definitions/flag 96 description: 97 If set, indicates that PHY will disable swap of the 98 TX/RX lanes. This property allows the PHY to work correcly after 99 e.g. wrong bootstrap configuration caused by issues in PCB 100 layout design. 101 102 eee-broken-100tx: 103 $ref: /schemas/types.yaml#/definitions/flag 104 description: 105 Mark the corresponding energy efficient ethernet mode as 106 broken and request the ethernet to stop advertising it. 107 108 eee-broken-1000t: 109 $ref: /schemas/types.yaml#/definitions/flag 110 description: 111 Mark the corresponding energy efficient ethernet mode as 112 broken and request the ethernet to stop advertising it. 113 114 eee-broken-10gt: 115 $ref: /schemas/types.yaml#/definitions/flag 116 description: 117 Mark the corresponding energy efficient ethernet mode as 118 broken and request the ethernet to stop advertising it. 119 120 eee-broken-1000kx: 121 $ref: /schemas/types.yaml#/definitions/flag 122 description: 123 Mark the corresponding energy efficient ethernet mode as 124 broken and request the ethernet to stop advertising it. 125 126 eee-broken-10gkx4: 127 $ref: /schemas/types.yaml#/definitions/flag 128 description: 129 Mark the corresponding energy efficient ethernet mode as 130 broken and request the ethernet to stop advertising it. 131 132 eee-broken-10gkr: 133 $ref: /schemas/types.yaml#/definitions/flag 134 description: 135 Mark the corresponding energy efficient ethernet mode as 136 broken and request the ethernet to stop advertising it. 137 138 phy-is-integrated: 139 $ref: /schemas/types.yaml#/definitions/flag 140 description: 141 If set, indicates that the PHY is integrated into the same 142 physical package as the Ethernet MAC. If needed, muxers 143 should be configured to ensure the integrated PHY is 144 used. The absence of this property indicates the muxers 145 should be configured so that the external PHY is used. 146 147 resets: 148 maxItems: 1 149 150 reset-names: 151 const: phy 152 153 reset-gpios: 154 maxItems: 1 155 description: 156 The GPIO phandle and specifier for the PHY reset signal. 157 158 reset-assert-us: 159 description: 160 Delay after the reset was asserted in microseconds. If this 161 property is missing the delay will be skipped. 162 163 reset-deassert-us: 164 description: 165 Delay after the reset was deasserted in microseconds. If 166 this property is missing the delay will be skipped. 167 168 sfp: 169 $ref: /schemas/types.yaml#/definitions/phandle 170 description: 171 Specifies a reference to a node representing a SFP cage. 172 173 rx-internal-delay-ps: 174 description: | 175 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for 176 PHY's that have configurable RX internal delays. If this property is 177 present then the PHY applies the RX delay. 178 179 tx-internal-delay-ps: 180 description: | 181 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for 182 PHY's that have configurable TX internal delays. If this property is 183 present then the PHY applies the TX delay. 184 185required: 186 - reg 187 188additionalProperties: true 189 190examples: 191 - | 192 ethernet { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 196 ethernet-phy@0 { 197 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45"; 198 interrupt-parent = <&PIC>; 199 interrupts = <35 1>; 200 reg = <0>; 201 202 resets = <&rst 8>; 203 reset-names = "phy"; 204 reset-gpios = <&gpio1 4 1>; 205 reset-assert-us = <1000>; 206 reset-deassert-us = <2000>; 207 }; 208 }; 209