1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Ethernet PHY Common Properties 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 13 14# The dt-schema tools will generate a select statement first by using 15# the compatible, and second by using the node name if any. In our 16# case, the node name is the one we want to match on, while the 17# compatible is optional. 18select: 19 properties: 20 $nodename: 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 22 23 required: 24 - $nodename 25 26properties: 27 $nodename: 28 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 29 30 compatible: 31 oneOf: 32 - const: ethernet-phy-ieee802.3-c22 33 description: PHYs that implement IEEE802.3 clause 22 34 - const: ethernet-phy-ieee802.3-c45 35 description: PHYs that implement IEEE802.3 clause 45 36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 37 description: 38 PHYs contain identification registers. These will be read to 39 identify the PHY. If the PHY reports an incorrect ID, or the 40 PHY requires a specific initialization sequence (like a 41 particular order of clocks, resets, power supplies), in 42 order to be able to read the ID registers, then the 43 compatible list must contain an entry with the correct PHY 44 ID in the above form. 45 The first group of digits is the 16 bit Phy Identifier 1 46 register, this is the chip vendor OUI bits 3:18. The 47 second group of digits is the Phy Identifier 2 register, 48 this is the chip vendor OUI bits 19:24, followed by 10 49 bits of a vendor specific ID. 50 - items: 51 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 52 - const: ethernet-phy-ieee802.3-c22 53 - items: 54 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" 55 - const: ethernet-phy-ieee802.3-c45 56 57 reg: 58 minimum: 0 59 maximum: 31 60 description: 61 The ID number for the PHY. 62 63 interrupts: 64 maxItems: 1 65 66 max-speed: 67 enum: 68 - 10 69 - 100 70 - 1000 71 - 2500 72 - 5000 73 - 10000 74 - 20000 75 - 25000 76 - 40000 77 - 50000 78 - 56000 79 - 100000 80 - 200000 81 description: 82 Maximum PHY supported speed in Mbits / seconds. 83 84 phy-10base-t1l-2.4vpp: 85 description: | 86 tristate, request/disable 2.4 Vpp operating mode. The values are: 87 0: Disable 2.4 Vpp operating mode. 88 1: Request 2.4 Vpp operating mode from link partner. 89 Absence of this property will leave configuration to default values. 90 $ref: /schemas/types.yaml#/definitions/uint32 91 enum: [0, 1] 92 93 broken-turn-around: 94 $ref: /schemas/types.yaml#/definitions/flag 95 description: 96 If set, indicates the PHY device does not correctly release 97 the turn around line low at end of the control phase of the 98 MDIO transaction. 99 100 brr-mode: 101 $ref: /schemas/types.yaml#/definitions/flag 102 description: 103 If set, indicates the network cable interface is an alternative one as 104 defined in the BroadR-Reach link mode specification under 1BR-100 and 105 1BR-10 names. The PHY must be configured to operate in BroadR-Reach mode 106 by software. 107 108 clocks: 109 maxItems: 1 110 description: 111 External clock connected to the PHY. If not specified it is assumed 112 that the PHY uses a fixed crystal or an internal oscillator. 113 114 enet-phy-lane-swap: 115 $ref: /schemas/types.yaml#/definitions/flag 116 description: 117 If set, indicates the PHY will swap the TX/RX lanes to 118 compensate for the board being designed with the lanes 119 swapped. 120 121 enet-phy-lane-no-swap: 122 $ref: /schemas/types.yaml#/definitions/flag 123 description: 124 If set, indicates that PHY will disable swap of the 125 TX/RX lanes. This property allows the PHY to work correctly after 126 e.g. wrong bootstrap configuration caused by issues in PCB 127 layout design. 128 129 enet-phy-pair-order: 130 $ref: /schemas/types.yaml#/definitions/uint32 131 enum: [0, 1] 132 description: 133 For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA). 134 135 eee-broken-100tx: 136 $ref: /schemas/types.yaml#/definitions/flag 137 description: 138 Mark the corresponding energy efficient ethernet mode as 139 broken and request the ethernet to stop advertising it. 140 141 eee-broken-1000t: 142 $ref: /schemas/types.yaml#/definitions/flag 143 description: 144 Mark the corresponding energy efficient ethernet mode as 145 broken and request the ethernet to stop advertising it. 146 147 eee-broken-10gt: 148 $ref: /schemas/types.yaml#/definitions/flag 149 description: 150 Mark the corresponding energy efficient ethernet mode as 151 broken and request the ethernet to stop advertising it. 152 153 eee-broken-1000kx: 154 $ref: /schemas/types.yaml#/definitions/flag 155 description: 156 Mark the corresponding energy efficient ethernet mode as 157 broken and request the ethernet to stop advertising it. 158 159 eee-broken-10gkx4: 160 $ref: /schemas/types.yaml#/definitions/flag 161 description: 162 Mark the corresponding energy efficient ethernet mode as 163 broken and request the ethernet to stop advertising it. 164 165 eee-broken-10gkr: 166 $ref: /schemas/types.yaml#/definitions/flag 167 description: 168 Mark the corresponding energy efficient ethernet mode as 169 broken and request the ethernet to stop advertising it. 170 171 timing-role: 172 $ref: /schemas/types.yaml#/definitions/string 173 enum: 174 - forced-master 175 - forced-slave 176 - preferred-master 177 - preferred-slave 178 description: | 179 Specifies the timing role of the PHY in the network link. This property is 180 required for setups where the role must be explicitly assigned via the 181 device tree due to limitations in hardware strapping or incorrect strap 182 configurations. 183 It is applicable to Single Pair Ethernet (1000/100/10Base-T1) and other 184 PHY types, including 1000Base-T, where it controls whether the PHY should 185 be a master (clock source) or a slave (clock receiver). 186 187 - 'forced-master': The PHY is forced to operate as a master. 188 - 'forced-slave': The PHY is forced to operate as a slave. 189 - 'preferred-master': Prefer the PHY to be master but allow negotiation. 190 - 'preferred-slave': Prefer the PHY to be slave but allow negotiation. 191 192 pses: 193 $ref: /schemas/types.yaml#/definitions/phandle-array 194 maxItems: 1 195 description: 196 Specifies a reference to a node representing a Power Sourcing Equipment. 197 198 phy-is-integrated: 199 $ref: /schemas/types.yaml#/definitions/flag 200 description: 201 If set, indicates that the PHY is integrated into the same 202 physical package as the Ethernet MAC. If needed, muxers 203 should be configured to ensure the integrated PHY is 204 used. The absence of this property indicates the muxers 205 should be configured so that the external PHY is used. 206 207 resets: 208 maxItems: 1 209 210 reset-names: 211 const: phy 212 213 reset-gpios: 214 maxItems: 1 215 description: 216 The GPIO phandle and specifier for the PHY reset signal. 217 218 reset-assert-us: 219 description: 220 Delay after the reset was asserted in microseconds. If this 221 property is missing the delay will be skipped. 222 223 reset-deassert-us: 224 description: 225 Delay after the reset was deasserted in microseconds. If 226 this property is missing the delay will be skipped. 227 228 sfp: 229 $ref: /schemas/types.yaml#/definitions/phandle 230 description: 231 Specifies a reference to a node representing a SFP cage. 232 233 rx-internal-delay-ps: 234 description: | 235 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for 236 PHY's that have configurable RX internal delays. If this property is 237 present then the PHY applies the RX delay. 238 239 tx-internal-delay-ps: 240 description: | 241 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for 242 PHY's that have configurable TX internal delays. If this property is 243 present then the PHY applies the TX delay. 244 245 tx-amplitude-100base-tx-percent: 246 description: 247 Transmit amplitude gain applied for 100BASE-TX. 100% matches 2V 248 peak-to-peak specified in ANSI X3.263. When omitted, the PHYs default 249 will be left as is. 250 251 mac-termination-ohms: 252 maximum: 200 253 description: 254 The xMII signals need series termination on the driver side to match both 255 the output driver impedance and the line characteristic impedance, to 256 prevent reflections and EMI problems. Select a resistance value which is 257 supported by the builtin resistors of the PHY, otherwise the resistors may 258 have to be placed on board. When omitted, the PHYs default will be left as 259 is. 260 261 leds: 262 type: object 263 264 properties: 265 '#address-cells': 266 const: 1 267 268 '#size-cells': 269 const: 0 270 271 patternProperties: 272 '^led@[a-f0-9]+$': 273 $ref: /schemas/leds/common.yaml# 274 275 properties: 276 reg: 277 maxItems: 1 278 description: 279 This defines the LED index in the PHY or the MAC. It's really 280 driver dependent and required for ports that define multiple 281 LED for the same port. 282 283 required: 284 - reg 285 286 unevaluatedProperties: false 287 288 additionalProperties: false 289 290 mdi: 291 type: object 292 293 patternProperties: 294 '^connector-[0-9]+$': 295 $ref: /schemas/net/ethernet-connector.yaml# 296 297 unevaluatedProperties: false 298 299 additionalProperties: false 300 301required: 302 - reg 303 304additionalProperties: true 305 306examples: 307 - | 308 #include <dt-bindings/leds/common.h> 309 310 ethernet { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 314 ethernet-phy@0 { 315 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45"; 316 interrupt-parent = <&PIC>; 317 interrupts = <35 1>; 318 reg = <0>; 319 320 resets = <&rst 8>; 321 reset-names = "phy"; 322 reset-gpios = <&gpio1 4 1>; 323 reset-assert-us = <1000>; 324 reset-deassert-us = <2000>; 325 326 leds { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 330 led@0 { 331 reg = <0>; 332 color = <LED_COLOR_ID_WHITE>; 333 function = LED_FUNCTION_LAN; 334 default-state = "keep"; 335 }; 336 }; 337 /* Fast Ethernet port, with only 2 pairs wired */ 338 mdi { 339 connector-0 { 340 pairs = <2>; 341 media = "BaseT"; 342 }; 343 }; 344 }; 345 }; 346