1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ethernet-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Ethernet Controller Generic Binding 8 9maintainers: 10 - David S. Miller <davem@davemloft.net> 11 12properties: 13 $nodename: 14 pattern: "^ethernet(@.*)?$" 15 16 label: 17 $ref: /schemas/types.yaml#/definitions/string 18 description: Human readable label on a port of a box. 19 20 local-mac-address: 21 description: 22 Specifies the MAC address that was assigned to the network device. 23 $ref: /schemas/types.yaml#/definitions/uint8-array 24 minItems: 6 25 maxItems: 6 26 27 mac-address: 28 description: 29 Specifies the MAC address that was last used by the boot 30 program; should be used in cases where the MAC address assigned 31 to the device by the boot program is different from the 32 local-mac-address property. 33 $ref: /schemas/types.yaml#/definitions/uint8-array 34 minItems: 6 35 maxItems: 6 36 37 max-frame-size: 38 $ref: /schemas/types.yaml#/definitions/uint32 39 description: 40 Maximum transfer unit (IEEE defined MTU), rather than the 41 maximum frame size (there\'s contradiction in the Devicetree 42 Specification). 43 44 max-speed: 45 $ref: /schemas/types.yaml#/definitions/uint32 46 description: 47 Specifies maximum speed in Mbit/s supported by the device. 48 49 nvmem-cells: 50 maxItems: 1 51 description: 52 Reference to an nvmem node for the MAC address 53 54 nvmem-cell-names: 55 const: mac-address 56 57 phy-connection-type: 58 description: 59 Specifies interface type between the Ethernet device and a physical 60 layer (PHY) device. 61 enum: 62 # There is not a standard bus between the MAC and the PHY, 63 # something proprietary is being used to embed the PHY in the 64 # MAC. 65 - internal 66 - mii 67 - gmii 68 - sgmii 69 - qsgmii 70 - tbi 71 - rev-mii 72 - rmii 73 - rev-rmii 74 - moca 75 76 # RX and TX delays are added by the MAC when required 77 - rgmii 78 79 # RGMII with internal RX and TX delays provided by the PHY, 80 # the MAC should not add the RX or TX delays in this case 81 - rgmii-id 82 83 # RGMII with internal RX delay provided by the PHY, the MAC 84 # should not add an RX delay in this case 85 - rgmii-rxid 86 87 # RGMII with internal TX delay provided by the PHY, the MAC 88 # should not add an TX delay in this case 89 - rgmii-txid 90 - rtbi 91 - smii 92 - xgmii 93 - trgmii 94 - 1000base-x 95 - 2500base-x 96 - 5gbase-r 97 - rxaui 98 - xaui 99 100 # 10GBASE-KR, XFI, SFI 101 - 10gbase-kr 102 - usxgmii 103 - 10gbase-r 104 - 25gbase-r 105 106 phy-mode: 107 $ref: "#/properties/phy-connection-type" 108 109 pcs-handle: 110 $ref: /schemas/types.yaml#/definitions/phandle 111 description: 112 Specifies a reference to a node representing a PCS PHY device on a MDIO 113 bus to link with an external PHY (phy-handle) if exists. 114 115 phy-handle: 116 $ref: /schemas/types.yaml#/definitions/phandle 117 description: 118 Specifies a reference to a node representing a PHY device. 119 120 phy: 121 $ref: "#/properties/phy-handle" 122 deprecated: true 123 124 phy-device: 125 $ref: "#/properties/phy-handle" 126 deprecated: true 127 128 rx-fifo-depth: 129 $ref: /schemas/types.yaml#/definitions/uint32 130 description: 131 The size of the controller\'s receive fifo in bytes. This is used 132 for components that can have configurable receive fifo sizes, 133 and is useful for determining certain configuration settings 134 such as flow control thresholds. 135 136 rx-internal-delay-ps: 137 description: | 138 RGMII Receive Clock Delay defined in pico seconds. 139 This is used for controllers that have configurable RX internal delays. 140 If this property is present then the MAC applies the RX delay. 141 142 sfp: 143 $ref: /schemas/types.yaml#/definitions/phandle 144 description: 145 Specifies a reference to a node representing a SFP cage. 146 147 tx-fifo-depth: 148 $ref: /schemas/types.yaml#/definitions/uint32 149 description: 150 The size of the controller\'s transmit fifo in bytes. This 151 is used for components that can have configurable fifo sizes. 152 153 tx-internal-delay-ps: 154 description: | 155 RGMII Transmit Clock Delay defined in pico seconds. 156 This is used for controllers that have configurable TX internal delays. 157 If this property is present then the MAC applies the TX delay. 158 159 managed: 160 description: 161 Specifies the PHY management type. If auto is set and fixed-link 162 is not specified, it uses MDIO for management. 163 $ref: /schemas/types.yaml#/definitions/string 164 default: auto 165 enum: 166 - auto 167 - in-band-status 168 169 fixed-link: 170 allOf: 171 - if: 172 type: array 173 then: 174 deprecated: true 175 items: 176 - minimum: 0 177 maximum: 31 178 description: 179 Emulated PHY ID, choose any but unique to the all 180 specified fixed-links 181 182 - enum: [0, 1] 183 description: 184 Duplex configuration. 0 for half duplex or 1 for 185 full duplex 186 187 - enum: [10, 100, 1000, 2500, 10000] 188 description: 189 Link speed in Mbits/sec. 190 191 - enum: [0, 1] 192 description: 193 Pause configuration. 0 for no pause, 1 for pause 194 195 - enum: [0, 1] 196 description: 197 Asymmetric pause configuration. 0 for no asymmetric 198 pause, 1 for asymmetric pause 199 200 201 - if: 202 type: object 203 then: 204 properties: 205 speed: 206 description: 207 Link speed. 208 $ref: /schemas/types.yaml#/definitions/uint32 209 enum: [10, 100, 1000, 2500, 10000] 210 211 full-duplex: 212 $ref: /schemas/types.yaml#/definitions/flag 213 description: 214 Indicates that full-duplex is used. When absent, half 215 duplex is assumed. 216 217 pause: 218 $ref: /schemas/types.yaml#definitions/flag 219 description: 220 Indicates that pause should be enabled. 221 222 asym-pause: 223 $ref: /schemas/types.yaml#/definitions/flag 224 description: 225 Indicates that asym_pause should be enabled. 226 227 link-gpios: 228 maxItems: 1 229 description: 230 GPIO to determine if the link is up 231 232 required: 233 - speed 234 235additionalProperties: true 236 237... 238