xref: /linux/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml (revision f6154d8babbb8a98f0d3ea325aafae2e33bfd8be) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/N1 Advanced 5 ports ethernet switch
8
9maintainers:
10  - Clément Léger <clement.leger@bootlin.com>
11
12description: |
13  The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
14  handles 4 ports + 1 CPU management port.
15
16allOf:
17  - $ref: dsa.yaml#/$defs/ethernet-ports
18
19properties:
20  compatible:
21    items:
22      - enum:
23          - renesas,r9a06g032-a5psw
24      - const: renesas,rzn1-a5psw
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    items:
31      - description: Device Level Ring (DLR) interrupt
32      - description: Switch interrupt
33      - description: Parallel Redundancy Protocol (PRP) interrupt
34      - description: Integrated HUB module interrupt
35      - description: Receive Pattern Match interrupt
36
37  interrupt-names:
38    items:
39      - const: dlr
40      - const: switch
41      - const: prp
42      - const: hub
43      - const: ptrn
44
45  power-domains:
46    maxItems: 1
47
48  mdio:
49    $ref: /schemas/net/mdio.yaml#
50    unevaluatedProperties: false
51
52  clocks:
53    items:
54      - description: AHB clock used for the switch register interface
55      - description: Switch system clock
56
57  clock-names:
58    items:
59      - const: hclk
60      - const: clk
61
62  ethernet-ports:
63    type: object
64    additionalProperties: true
65    patternProperties:
66      "^(ethernet-)?port@[0-4]$":
67        type: object
68        additionalProperties: true
69        properties:
70          pcs-handle:
71            maxItems: 1
72            description:
73              phandle pointing to a PCS sub-node compatible with
74              renesas,rzn1-miic.yaml#
75
76unevaluatedProperties: false
77
78required:
79  - compatible
80  - reg
81  - clocks
82  - clock-names
83  - power-domains
84
85examples:
86  - |
87    #include <dt-bindings/gpio/gpio.h>
88    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90
91    switch@44050000 {
92        compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
93        reg = <0x44050000 0x10000>;
94        clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;
95        clock-names = "hclk", "clk";
96        power-domains = <&sysctrl>;
97        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
98                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
99                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
100                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
101                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
102        interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
103
104        dsa,member = <0 0>;
105
106        ethernet-ports {
107            #address-cells = <1>;
108            #size-cells = <0>;
109
110            port@0 {
111                reg = <0>;
112                label = "lan0";
113                phy-handle = <&switch0phy3>;
114                pcs-handle = <&mii_conv4>;
115            };
116
117            port@1 {
118                reg = <1>;
119                label = "lan1";
120                phy-handle = <&switch0phy1>;
121                pcs-handle = <&mii_conv3>;
122            };
123
124            port@4 {
125                reg = <4>;
126                ethernet = <&gmac2>;
127                phy-mode = "internal";
128
129                fixed-link {
130                  speed = <1000>;
131                  full-duplex;
132                };
133            };
134        };
135
136        mdio {
137            #address-cells = <1>;
138            #size-cells = <0>;
139
140            reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
141            reset-delay-us = <15>;
142            clock-frequency = <2500000>;
143
144            switch0phy1: ethernet-phy@1{
145                reg = <1>;
146            };
147
148            switch0phy3: ethernet-phy@3{
149                reg = <3>;
150            };
151        };
152    };
153