1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP SJA1105 Automotive Ethernet Switch Family 8 9description: 10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at 11 least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum 12 cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed 13 depends on the SPI bus master driver. 14 15maintainers: 16 - Vladimir Oltean <vladimir.oltean@nxp.com> 17 18properties: 19 compatible: 20 enum: 21 - nxp,sja1105e 22 - nxp,sja1105t 23 - nxp,sja1105p 24 - nxp,sja1105q 25 - nxp,sja1105r 26 - nxp,sja1105s 27 - nxp,sja1110a 28 - nxp,sja1110b 29 - nxp,sja1110c 30 - nxp,sja1110d 31 32 reg: 33 maxItems: 1 34 35 reset-gpios: 36 description: 37 A GPIO connected to the active-low RST_N pin of the SJA1105. Note that 38 reset of this chip is performed via SPI and the RST_N pin must be wired 39 to satisfy the power-up sequence documented in "SJA1105PQRS Application 40 Hints" (AH1704) sec. 2.4.4. Connecting the SJA1105 RST_N pin to a GPIO is 41 therefore discouraged. 42 maxItems: 1 43 44 spi-cpha: true 45 spi-cpol: true 46 47 # Optional container node for the 2 internal MDIO buses of the SJA1110 48 # (one for the internal 100base-T1 PHYs and the other for the single 49 # 100base-TX PHY). The "reg" property does not have physical significance. 50 # The PHY addresses to port correspondence is as follows: for 100base-T1, 51 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has 52 # PHY 1. 53 mdios: 54 type: object 55 additionalProperties: false 56 57 properties: 58 '#address-cells': 59 const: 1 60 '#size-cells': 61 const: 0 62 63 patternProperties: 64 "^mdio@[0-1]$": 65 $ref: /schemas/net/mdio.yaml# 66 unevaluatedProperties: false 67 68 properties: 69 compatible: 70 oneOf: 71 - enum: 72 - nxp,sja1110-base-t1-mdio 73 - nxp,sja1110-base-tx-mdio 74 75 reg: 76 oneOf: 77 - enum: 78 - 0 79 - 1 80 81 required: 82 - compatible 83 - reg 84 85patternProperties: 86 "^(ethernet-)?ports$": 87 additionalProperties: true 88 patternProperties: 89 "^(ethernet-)?port@[0-9]$": 90 allOf: 91 - if: 92 properties: 93 phy-mode: 94 contains: 95 enum: 96 - rgmii 97 - rgmii-rxid 98 - rgmii-txid 99 - rgmii-id 100 then: 101 properties: 102 rx-internal-delay-ps: 103 $ref: "#/$defs/internal-delay-ps" 104 tx-internal-delay-ps: 105 $ref: "#/$defs/internal-delay-ps" 106 107required: 108 - compatible 109 - reg 110 111$defs: 112 internal-delay-ps: 113 description: 114 Disable tunable delay lines using 0 ps, or enable them and select 115 the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps 116 (101.7 degree shift) in increments of 0.9 degrees (20 ps). 117 enum: 118 [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840, 119 1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080, 120 2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260] 121 122allOf: 123 - $ref: dsa.yaml#/$defs/ethernet-ports 124 - $ref: /schemas/spi/spi-peripheral-props.yaml# 125 - if: 126 properties: 127 compatible: 128 enum: 129 - nxp,sja1105e 130 - nxp,sja1105p 131 - nxp,sja1105q 132 - nxp,sja1105r 133 - nxp,sja1105s 134 - nxp,sja1105t 135 then: 136 properties: 137 spi-cpol: false 138 required: 139 - spi-cpha 140 else: 141 properties: 142 spi-cpha: false 143 required: 144 - spi-cpol 145 146unevaluatedProperties: false 147 148examples: 149 - | 150 spi { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 ethernet-switch@1 { 155 reg = <0x1>; 156 compatible = "nxp,sja1105t"; 157 spi-cpha; 158 159 ethernet-ports { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 163 port@0 { 164 phy-handle = <&rgmii_phy6>; 165 phy-mode = "rgmii-id"; 166 rx-internal-delay-ps = <0>; 167 tx-internal-delay-ps = <0>; 168 reg = <0>; 169 }; 170 171 port@1 { 172 phy-handle = <&rgmii_phy3>; 173 phy-mode = "rgmii-id"; 174 rx-internal-delay-ps = <0>; 175 tx-internal-delay-ps = <0>; 176 reg = <1>; 177 }; 178 179 port@2 { 180 phy-handle = <&rgmii_phy4>; 181 phy-mode = "rgmii-id"; 182 rx-internal-delay-ps = <0>; 183 tx-internal-delay-ps = <0>; 184 reg = <2>; 185 }; 186 187 port@3 { 188 phy-handle = <&rgmii_phy4>; 189 phy-mode = "rgmii-id"; 190 rx-internal-delay-ps = <0>; 191 tx-internal-delay-ps = <0>; 192 reg = <3>; 193 }; 194 195 port@4 { 196 ethernet = <&enet2>; 197 phy-mode = "rgmii"; 198 rx-internal-delay-ps = <0>; 199 tx-internal-delay-ps = <0>; 200 reg = <4>; 201 202 fixed-link { 203 speed = <1000>; 204 full-duplex; 205 }; 206 }; 207 }; 208 }; 209 }; 210