xref: /linux/Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml (revision 8ca4fc323d2e4ab9dabbdd57633af40b0c7e6af9) 
1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip Ocelot Switch Family Device Tree Bindings
8
9maintainers:
10  - Vladimir Oltean <vladimir.oltean@nxp.com>
11  - Claudiu Manoil <claudiu.manoil@nxp.com>
12  - Alexandre Belloni <alexandre.belloni@bootlin.com>
13  - UNGLinuxDriver@microchip.com
14
15description: |
16  There are multiple switches which are either part of the Ocelot-1 family, or
17  derivatives of this architecture. These switches can be found embedded in
18  various SoCs and accessed using MMIO, or as discrete chips and accessed over
19  SPI or PCIe. The present DSA binding shall be used when the host controlling
20  them performs packet I/O primarily through an Ethernet port of the switch
21  (which is attached to an Ethernet port of the host), rather than through
22  Frame DMA or register-based I/O.
23
24  VSC9953 (Seville):
25
26    This is found in the NXP T1040, where it is a memory-mapped platform
27    device.
28
29    The following PHY interface types are supported:
30
31      - phy-mode = "internal": on ports 8 and 9
32      - phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
33      - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
34      - phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7
35
36  VSC9959 (Felix):
37
38    This is found in the NXP LS1028A. It is a PCI device, part of the larger
39    enetc root complex. As a result, the ethernet-switch node is a sub-node of
40    the PCIe root complex node and its "reg" property conforms to the parent
41    node bindings, describing it as PF 5 of device 0, bus 0.
42
43    If any external switch port is enabled, the enetc PF2 (enetc_port2) should
44    be enabled as well. This is because the internal MDIO bus (exposed through
45    EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
46    port 2 and not to Felix.
47
48    The following PHY interface types are supported:
49
50      - phy-mode = "internal": on ports 4 and 5
51      - phy-mode = "sgmii": on ports 0, 1, 2, 3
52      - phy-mode = "qsgmii": on ports 0, 1, 2, 3
53      - phy-mode = "usxgmii": on ports 0, 1, 2, 3
54      - phy-mode = "1000base-x": on ports 0, 1, 2, 3
55      - phy-mode = "2500base-x": on ports 0, 1, 2, 3
56
57properties:
58  compatible:
59    enum:
60      - mscc,vsc9953-switch
61      - pci1957,eef0
62
63  reg:
64    maxItems: 1
65
66  interrupts:
67    maxItems: 1
68
69    description:
70      Used to signal availability of PTP TX timestamps, and state changes of
71      the MAC merge layer of ports that support Frame Preemption.
72
73  little-endian: true
74  big-endian: true
75
76required:
77  - compatible
78  - reg
79
80allOf:
81  - $ref: dsa.yaml#
82  - if:
83      properties:
84        compatible:
85          const: pci1957,eef0
86    then:
87      required:
88        - interrupts
89
90unevaluatedProperties: false
91
92examples:
93  # Felix VSC9959 (NXP LS1028A)
94  - |
95    #include <dt-bindings/interrupt-controller/arm-gic.h>
96
97    pcie { /* Integrated Endpoint Root Complex */
98        #address-cells = <3>;
99        #size-cells = <2>;
100
101        ethernet-switch@0,5 {
102            compatible = "pci1957,eef0";
103            reg = <0x000500 0 0 0 0>;
104            interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
105
106            ethernet-ports {
107                #address-cells = <1>;
108                #size-cells = <0>;
109
110                port@0 {
111                    reg = <0>;
112                    phy-mode = "qsgmii";
113                    phy-handle = <&phy0>;
114                    managed = "in-band-status";
115                };
116
117                port@1 {
118                    reg = <1>;
119                    phy-mode = "qsgmii";
120                    phy-handle = <&phy1>;
121                    managed = "in-band-status";
122                };
123
124                port@2 {
125                    reg = <2>;
126                    phy-mode = "qsgmii";
127                    phy-handle = <&phy2>;
128                    managed = "in-band-status";
129                };
130
131                port@3 {
132                    reg = <3>;
133                    phy-mode = "qsgmii";
134                    phy-handle = <&phy3>;
135                    managed = "in-band-status";
136                };
137
138                port@4 {
139                    reg = <4>;
140                    ethernet = <&enetc_port2>;
141                    phy-mode = "internal";
142
143                    fixed-link {
144                        speed = <2500>;
145                        full-duplex;
146                        pause;
147                    };
148                };
149
150                port@5 {
151                    reg = <5>;
152                    ethernet = <&enetc_port3>;
153                    phy-mode = "internal";
154
155                    fixed-link {
156                        speed = <1000>;
157                        full-duplex;
158                        pause;
159                    };
160                };
161            };
162        };
163    };
164  # Seville VSC9953 (NXP T1040)
165  - |
166    soc {
167        #address-cells = <1>;
168        #size-cells = <1>;
169
170        ethernet-switch@800000 {
171            compatible = "mscc,vsc9953-switch";
172            reg = <0x800000 0x290000>;
173            little-endian;
174
175            ethernet-ports {
176                #address-cells = <1>;
177                #size-cells = <0>;
178
179                port@0 {
180                    reg = <0>;
181                    phy-mode = "qsgmii";
182                    phy-handle = <&phy0>;
183                    managed = "in-band-status";
184                };
185
186                port@1 {
187                    reg = <1>;
188                    phy-mode = "qsgmii";
189                    phy-handle = <&phy1>;
190                    managed = "in-band-status";
191                };
192
193                port@2 {
194                    reg = <2>;
195                    phy-mode = "qsgmii";
196                    phy-handle = <&phy2>;
197                    managed = "in-band-status";
198                };
199
200                port@3 {
201                    reg = <3>;
202                    phy-mode = "qsgmii";
203                    phy-handle = <&phy3>;
204                    managed = "in-band-status";
205                };
206
207                port@4 {
208                    reg = <4>;
209                    phy-mode = "qsgmii";
210                    phy-handle = <&phy4>;
211                    managed = "in-band-status";
212                };
213
214                port@5 {
215                    reg = <5>;
216                    phy-mode = "qsgmii";
217                    phy-handle = <&phy5>;
218                    managed = "in-band-status";
219                };
220
221                port@6 {
222                    reg = <6>;
223                    phy-mode = "qsgmii";
224                    phy-handle = <&phy6>;
225                    managed = "in-band-status";
226                };
227
228                port@7 {
229                    reg = <7>;
230                    phy-mode = "qsgmii";
231                    phy-handle = <&phy7>;
232                    managed = "in-band-status";
233                };
234
235                port@8 {
236                    reg = <8>;
237                    phy-mode = "internal";
238                    ethernet = <&enet0>;
239
240                    fixed-link {
241                        speed = <2500>;
242                        full-duplex;
243                        pause;
244                    };
245                };
246
247                port@9 {
248                    reg = <9>;
249                    phy-mode = "internal";
250                    ethernet = <&enet1>;
251
252                    fixed-link {
253                        speed = <2500>;
254                        full-duplex;
255                        pause;
256                    };
257                };
258            };
259        };
260    };
261