xref: /linux/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip KSZ Series Ethernet switches
8
9maintainers:
10  - Marek Vasut <marex@denx.de>
11  - Woojung Huh <Woojung.Huh@microchip.com>
12
13allOf:
14  - $ref: /schemas/spi/spi-peripheral-props.yaml#
15
16properties:
17  # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
18  # required and optional properties.
19  compatible:
20    enum:
21      - microchip,ksz8463
22      - microchip,ksz8765
23      - microchip,ksz8794
24      - microchip,ksz8795
25      - microchip,ksz8863
26      - microchip,ksz8864  # 4-port version of KSZ8895 family switch
27      - microchip,ksz8873
28      - microchip,ksz8895  # 5-port version of KSZ8895 family switch
29      - microchip,ksz9477
30      - microchip,ksz9897
31      - microchip,ksz9896
32      - microchip,ksz9567
33      - microchip,ksz8565
34      - microchip,ksz9893
35      - microchip,ksz9563
36      - microchip,ksz8563
37      - microchip,ksz8567
38      - microchip,lan9646
39
40  reset-gpios:
41    description:
42      Should be a gpio specifier for a reset line.
43    maxItems: 1
44
45  wakeup-source: true
46
47  microchip,synclko-125:
48    $ref: /schemas/types.yaml#/definitions/flag
49    description:
50      Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
51
52  microchip,synclko-disable:
53    $ref: /schemas/types.yaml#/definitions/flag
54    description:
55      Set if the output SYNCLKO clock should be disabled. Do not mix with
56      microchip,synclko-125.
57
58  microchip,pme-active-high:
59    $ref: /schemas/types.yaml#/definitions/flag
60    description:
61      Indicates if the PME pin polarity is active-high.
62
63  microchip,io-drive-strength-microamp:
64    description:
65      IO Pad Drive Strength
66    enum: [8000, 16000]
67    default: 16000
68
69  microchip,hi-drive-strength-microamp:
70    description:
71      High Speed Drive Strength. Controls drive strength of GMII / RGMII /
72      MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
73    enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
74    default: 24000
75
76  microchip,lo-drive-strength-microamp:
77    description:
78      Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
79      COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
80    enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
81    default: 8000
82
83  interrupts:
84    maxItems: 1
85
86  mdio:
87    $ref: /schemas/net/mdio.yaml#
88    unevaluatedProperties: false
89    properties:
90      mdio-parent-bus:
91        $ref: /schemas/types.yaml#/definitions/phandle
92        description:
93          Phandle pointing to the MDIO bus controller connected to the
94          secondary MDIO interface. This property should be used when
95          the internal MDIO bus is accessed via a secondary MDIO
96          interface rather than the primary management interface.
97
98    patternProperties:
99      "^ethernet-phy@[0-9a-f]$":
100        type: object
101        $ref: /schemas/net/ethernet-phy.yaml#
102        unevaluatedProperties: false
103        description:
104          Integrated PHY node
105
106required:
107  - compatible
108  - reg
109
110if:
111  not:
112    properties:
113      compatible:
114        enum:
115          - microchip,ksz8863
116          - microchip,ksz8873
117then:
118  $ref: dsa.yaml#/$defs/ethernet-ports
119else:
120  patternProperties:
121    "^(ethernet-)?ports$":
122      patternProperties:
123        "^(ethernet-)?port@[0-2]$":
124          $ref: dsa-port.yaml#
125          unevaluatedProperties: false
126          properties:
127            microchip,rmii-clk-internal:
128              $ref: /schemas/types.yaml#/definitions/flag
129              description:
130                When ksz88x3 is acting as clock provier (via REFCLKO) it
131                can select between internal and external RMII reference
132                clock. Internal reference clock means that the clock for
133                the RMII of ksz88x3 is provided by the ksz88x3 internally
134                and the REFCLKI pin is unconnected. For the external
135                reference clock, the clock needs to be fed back to ksz88x3
136                via REFCLKI.
137                If microchip,rmii-clk-internal is set, ksz88x3 will provide
138                rmii reference clock internally, otherwise reference clock
139                should be provided externally.
140          dependencies:
141            microchip,rmii-clk-internal: [ethernet]
142
143unevaluatedProperties: false
144
145examples:
146  - |
147    #include <dt-bindings/gpio/gpio.h>
148
149    // Ethernet switch connected via SPI to the host, CPU port wired to eth0:
150    eth0 {
151        fixed-link {
152            speed = <1000>;
153            full-duplex;
154        };
155    };
156
157    spi {
158        #address-cells = <1>;
159        #size-cells = <0>;
160
161        pinctrl-0 = <&pinctrl_spi_ksz>;
162        cs-gpios = <&pioC 25 0>;
163
164        ksz9477: switch@0 {
165            compatible = "microchip,ksz9477";
166            reg = <0>;
167            reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
168
169            spi-max-frequency = <44000000>;
170
171            ethernet-ports {
172                #address-cells = <1>;
173                #size-cells = <0>;
174                port@0 {
175                    reg = <0>;
176                    label = "lan1";
177                };
178                port@1 {
179                    reg = <1>;
180                    label = "lan2";
181                };
182                port@2 {
183                    reg = <2>;
184                    label = "lan3";
185                };
186                port@3 {
187                    reg = <3>;
188                    label = "lan4";
189                };
190                port@4 {
191                    reg = <4>;
192                    label = "lan5";
193                };
194                port@5 {
195                    reg = <5>;
196                    ethernet = <&eth0>;
197                    phy-mode = "rgmii";
198
199                    fixed-link {
200                        speed = <1000>;
201                        full-duplex;
202                    };
203                };
204            };
205        };
206
207        ksz8565: switch@1 {
208            compatible = "microchip,ksz8565";
209            reg = <1>;
210
211            spi-max-frequency = <44000000>;
212
213            ethernet-ports {
214                #address-cells = <1>;
215                #size-cells = <0>;
216                port@0 {
217                    reg = <0>;
218                    label = "lan1";
219                };
220                port@1 {
221                    reg = <1>;
222                    label = "lan2";
223                };
224                port@2 {
225                    reg = <2>;
226                    label = "lan3";
227                };
228                port@3 {
229                    reg = <3>;
230                    label = "lan4";
231                };
232                port@6 {
233                    reg = <6>;
234                    ethernet = <&eth0>;
235                    phy-mode = "rgmii";
236
237                    fixed-link {
238                        speed = <1000>;
239                        full-duplex;
240                    };
241                };
242            };
243        };
244    };
245...
246