xref: /linux/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml (revision 9cc8d0ecdd2aad42e377e971e3bb114339df609e) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip KSZ Series Ethernet switches
8
9maintainers:
10  - Marek Vasut <marex@denx.de>
11  - Woojung Huh <Woojung.Huh@microchip.com>
12
13allOf:
14  - $ref: /schemas/spi/spi-peripheral-props.yaml#
15
16properties:
17  # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
18  # required and optional properties.
19  compatible:
20    enum:
21      - microchip,ksz8765
22      - microchip,ksz8794
23      - microchip,ksz8795
24      - microchip,ksz8863
25      - microchip,ksz8864  # 4-port version of KSZ8895 family switch
26      - microchip,ksz8873
27      - microchip,ksz8895  # 5-port version of KSZ8895 family switch
28      - microchip,ksz9477
29      - microchip,ksz9897
30      - microchip,ksz9896
31      - microchip,ksz9567
32      - microchip,ksz8565
33      - microchip,ksz9893
34      - microchip,ksz9563
35      - microchip,ksz8563
36      - microchip,ksz8567
37      - microchip,lan9646
38
39  reset-gpios:
40    description:
41      Should be a gpio specifier for a reset line.
42    maxItems: 1
43
44  wakeup-source: true
45
46  microchip,synclko-125:
47    $ref: /schemas/types.yaml#/definitions/flag
48    description:
49      Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
50
51  microchip,synclko-disable:
52    $ref: /schemas/types.yaml#/definitions/flag
53    description:
54      Set if the output SYNCLKO clock should be disabled. Do not mix with
55      microchip,synclko-125.
56
57  microchip,pme-active-high:
58    $ref: /schemas/types.yaml#/definitions/flag
59    description:
60      Indicates if the PME pin polarity is active-high.
61
62  microchip,io-drive-strength-microamp:
63    description:
64      IO Pad Drive Strength
65    enum: [8000, 16000]
66    default: 16000
67
68  microchip,hi-drive-strength-microamp:
69    description:
70      High Speed Drive Strength. Controls drive strength of GMII / RGMII /
71      MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
72    enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
73    default: 24000
74
75  microchip,lo-drive-strength-microamp:
76    description:
77      Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
78      COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
79    enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
80    default: 8000
81
82  interrupts:
83    maxItems: 1
84
85  mdio:
86    $ref: /schemas/net/mdio.yaml#
87    unevaluatedProperties: false
88    properties:
89      mdio-parent-bus:
90        $ref: /schemas/types.yaml#/definitions/phandle
91        description:
92          Phandle pointing to the MDIO bus controller connected to the
93          secondary MDIO interface. This property should be used when
94          the internal MDIO bus is accessed via a secondary MDIO
95          interface rather than the primary management interface.
96
97    patternProperties:
98      "^ethernet-phy@[0-9a-f]$":
99        type: object
100        $ref: /schemas/net/ethernet-phy.yaml#
101        unevaluatedProperties: false
102        description:
103          Integrated PHY node
104
105required:
106  - compatible
107  - reg
108
109if:
110  not:
111    properties:
112      compatible:
113        enum:
114          - microchip,ksz8863
115          - microchip,ksz8873
116then:
117  $ref: dsa.yaml#/$defs/ethernet-ports
118else:
119  patternProperties:
120    "^(ethernet-)?ports$":
121      patternProperties:
122        "^(ethernet-)?port@[0-2]$":
123          $ref: dsa-port.yaml#
124          unevaluatedProperties: false
125          properties:
126            microchip,rmii-clk-internal:
127              $ref: /schemas/types.yaml#/definitions/flag
128              description:
129                When ksz88x3 is acting as clock provier (via REFCLKO) it
130                can select between internal and external RMII reference
131                clock. Internal reference clock means that the clock for
132                the RMII of ksz88x3 is provided by the ksz88x3 internally
133                and the REFCLKI pin is unconnected. For the external
134                reference clock, the clock needs to be fed back to ksz88x3
135                via REFCLKI.
136                If microchip,rmii-clk-internal is set, ksz88x3 will provide
137                rmii reference clock internally, otherwise reference clock
138                should be provided externally.
139          dependencies:
140            microchip,rmii-clk-internal: [ethernet]
141
142unevaluatedProperties: false
143
144examples:
145  - |
146    #include <dt-bindings/gpio/gpio.h>
147
148    // Ethernet switch connected via SPI to the host, CPU port wired to eth0:
149    eth0 {
150        fixed-link {
151            speed = <1000>;
152            full-duplex;
153        };
154    };
155
156    spi {
157        #address-cells = <1>;
158        #size-cells = <0>;
159
160        pinctrl-0 = <&pinctrl_spi_ksz>;
161        cs-gpios = <&pioC 25 0>;
162
163        ksz9477: switch@0 {
164            compatible = "microchip,ksz9477";
165            reg = <0>;
166            reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
167
168            spi-max-frequency = <44000000>;
169
170            ethernet-ports {
171                #address-cells = <1>;
172                #size-cells = <0>;
173                port@0 {
174                    reg = <0>;
175                    label = "lan1";
176                };
177                port@1 {
178                    reg = <1>;
179                    label = "lan2";
180                };
181                port@2 {
182                    reg = <2>;
183                    label = "lan3";
184                };
185                port@3 {
186                    reg = <3>;
187                    label = "lan4";
188                };
189                port@4 {
190                    reg = <4>;
191                    label = "lan5";
192                };
193                port@5 {
194                    reg = <5>;
195                    ethernet = <&eth0>;
196                    phy-mode = "rgmii";
197
198                    fixed-link {
199                        speed = <1000>;
200                        full-duplex;
201                    };
202                };
203            };
204        };
205
206        ksz8565: switch@1 {
207            compatible = "microchip,ksz8565";
208            reg = <1>;
209
210            spi-max-frequency = <44000000>;
211
212            ethernet-ports {
213                #address-cells = <1>;
214                #size-cells = <0>;
215                port@0 {
216                    reg = <0>;
217                    label = "lan1";
218                };
219                port@1 {
220                    reg = <1>;
221                    label = "lan2";
222                };
223                port@2 {
224                    reg = <2>;
225                    label = "lan3";
226                };
227                port@3 {
228                    reg = <3>;
229                    label = "lan4";
230                };
231                port@6 {
232                    reg = <6>;
233                    ethernet = <&eth0>;
234                    phy-mode = "rgmii";
235
236                    fixed-link {
237                        speed = <1000>;
238                        full-duplex;
239                    };
240                };
241            };
242        };
243    };
244...
245