1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip KSZ Series Ethernet switches 8 9maintainers: 10 - Marek Vasut <marex@denx.de> 11 - Woojung Huh <Woojung.Huh@microchip.com> 12 13properties: 14 # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional 15 # required and optional properties. 16 compatible: 17 enum: 18 - microchip,ksz8463 19 - microchip,ksz8765 20 - microchip,ksz8794 21 - microchip,ksz8795 22 - microchip,ksz8863 23 - microchip,ksz8864 # 4-port version of KSZ8895 family switch 24 - microchip,ksz8873 25 - microchip,ksz8895 # 5-port version of KSZ8895 family switch 26 - microchip,ksz9477 27 - microchip,ksz9897 28 - microchip,ksz9896 29 - microchip,ksz9567 30 - microchip,ksz8565 31 - microchip,ksz9893 32 - microchip,ksz9563 33 - microchip,ksz8563 34 - microchip,ksz8567 35 - microchip,lan9646 36 37 pinctrl-names: 38 items: 39 - const: default 40 - const: reset 41 description: 42 Used during reset for strap configuration. 43 44 reset-gpios: 45 description: 46 Should be a gpio specifier for a reset line. 47 maxItems: 1 48 49 wakeup-source: true 50 51 microchip,synclko-125: 52 $ref: /schemas/types.yaml#/definitions/flag 53 description: 54 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz. 55 56 microchip,synclko-disable: 57 $ref: /schemas/types.yaml#/definitions/flag 58 description: 59 Set if the output SYNCLKO clock should be disabled. Do not mix with 60 microchip,synclko-125. 61 62 microchip,pme-active-high: 63 $ref: /schemas/types.yaml#/definitions/flag 64 description: 65 Indicates if the PME pin polarity is active-high. 66 67 microchip,io-drive-strength-microamp: 68 description: 69 IO Pad Drive Strength 70 enum: [8000, 16000] 71 default: 16000 72 73 microchip,hi-drive-strength-microamp: 74 description: 75 High Speed Drive Strength. Controls drive strength of GMII / RGMII / 76 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines. 77 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000] 78 default: 24000 79 80 microchip,lo-drive-strength-microamp: 81 description: 82 Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI, 83 COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines. 84 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000] 85 default: 8000 86 87 interrupts: 88 maxItems: 1 89 90 mdio: 91 $ref: /schemas/net/mdio.yaml# 92 unevaluatedProperties: false 93 properties: 94 mdio-parent-bus: 95 $ref: /schemas/types.yaml#/definitions/phandle 96 description: 97 Phandle pointing to the MDIO bus controller connected to the 98 secondary MDIO interface. This property should be used when 99 the internal MDIO bus is accessed via a secondary MDIO 100 interface rather than the primary management interface. 101 102 patternProperties: 103 "^ethernet-phy@[0-9a-f]$": 104 type: object 105 $ref: /schemas/net/ethernet-phy.yaml# 106 unevaluatedProperties: false 107 description: 108 Integrated PHY node 109 110required: 111 - compatible 112 - reg 113 114allOf: 115 - $ref: /schemas/spi/spi-peripheral-props.yaml# 116 117 - if: 118 not: 119 properties: 120 compatible: 121 enum: 122 - microchip,ksz8863 123 - microchip,ksz8873 124 then: 125 $ref: dsa.yaml#/$defs/ethernet-ports 126 else: 127 patternProperties: 128 "^(ethernet-)?ports$": 129 patternProperties: 130 "^(ethernet-)?port@[0-2]$": 131 $ref: dsa-port.yaml# 132 unevaluatedProperties: false 133 properties: 134 microchip,rmii-clk-internal: 135 $ref: /schemas/types.yaml#/definitions/flag 136 description: 137 When ksz88x3 is acting as clock provier (via REFCLKO) it 138 can select between internal and external RMII reference 139 clock. Internal reference clock means that the clock for 140 the RMII of ksz88x3 is provided by the ksz88x3 internally 141 and the REFCLKI pin is unconnected. For the external 142 reference clock, the clock needs to be fed back to ksz88x3 143 via REFCLKI. 144 If microchip,rmii-clk-internal is set, ksz88x3 will provide 145 rmii reference clock internally, otherwise reference clock 146 should be provided externally. 147 dependencies: 148 microchip,rmii-clk-internal: [ethernet] 149 - if: 150 properties: 151 compatible: 152 contains: 153 const: microchip,ksz8463 154 then: 155 properties: 156 straps-rxd-gpios: 157 description: 158 RXD0 and RXD1 pins, used to select SPI as bus interface. 159 minItems: 2 160 maxItems: 2 161 162unevaluatedProperties: false 163 164examples: 165 - | 166 #include <dt-bindings/gpio/gpio.h> 167 168 // Ethernet switch connected via SPI to the host, CPU port wired to eth0: 169 eth0 { 170 fixed-link { 171 speed = <1000>; 172 full-duplex; 173 }; 174 }; 175 176 spi { 177 #address-cells = <1>; 178 #size-cells = <0>; 179 180 pinctrl-0 = <&pinctrl_spi_ksz>; 181 cs-gpios = <&pioC 25 0>; 182 183 ksz9477: switch@0 { 184 compatible = "microchip,ksz9477"; 185 reg = <0>; 186 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 187 188 spi-max-frequency = <44000000>; 189 190 ethernet-ports { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 port@0 { 194 reg = <0>; 195 label = "lan1"; 196 }; 197 port@1 { 198 reg = <1>; 199 label = "lan2"; 200 }; 201 port@2 { 202 reg = <2>; 203 label = "lan3"; 204 }; 205 port@3 { 206 reg = <3>; 207 label = "lan4"; 208 }; 209 port@4 { 210 reg = <4>; 211 label = "lan5"; 212 }; 213 port@5 { 214 reg = <5>; 215 ethernet = <ð0>; 216 phy-mode = "rgmii"; 217 218 fixed-link { 219 speed = <1000>; 220 full-duplex; 221 }; 222 }; 223 }; 224 }; 225 226 ksz8565: switch@1 { 227 compatible = "microchip,ksz8565"; 228 reg = <1>; 229 230 spi-max-frequency = <44000000>; 231 232 ethernet-ports { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 port@0 { 236 reg = <0>; 237 label = "lan1"; 238 }; 239 port@1 { 240 reg = <1>; 241 label = "lan2"; 242 }; 243 port@2 { 244 reg = <2>; 245 label = "lan3"; 246 }; 247 port@3 { 248 reg = <3>; 249 label = "lan4"; 250 }; 251 port@6 { 252 reg = <6>; 253 ethernet = <ð0>; 254 phy-mode = "rgmii"; 255 256 fixed-link { 257 speed = <1000>; 258 full-duplex; 259 }; 260 }; 261 }; 262 }; 263 }; 264... 265