xref: /linux/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml (revision 12079a59ce52e72a342c49cfacf0281213fd6f32) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip KSZ Series Ethernet switches
8
9maintainers:
10  - Marek Vasut <marex@denx.de>
11  - Woojung Huh <Woojung.Huh@microchip.com>
12
13allOf:
14  - $ref: /schemas/spi/spi-peripheral-props.yaml#
15
16properties:
17  # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
18  # required and optional properties.
19  compatible:
20    enum:
21      - microchip,ksz8765
22      - microchip,ksz8794
23      - microchip,ksz8795
24      - microchip,ksz8863
25      - microchip,ksz8864  # 4-port version of KSZ8895 family switch
26      - microchip,ksz8873
27      - microchip,ksz8895  # 5-port version of KSZ8895 family switch
28      - microchip,ksz9477
29      - microchip,ksz9897
30      - microchip,ksz9896
31      - microchip,ksz9567
32      - microchip,ksz8565
33      - microchip,ksz9893
34      - microchip,ksz9563
35      - microchip,ksz8563
36      - microchip,ksz8567
37
38  reset-gpios:
39    description:
40      Should be a gpio specifier for a reset line.
41    maxItems: 1
42
43  wakeup-source: true
44
45  microchip,synclko-125:
46    $ref: /schemas/types.yaml#/definitions/flag
47    description:
48      Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
49
50  microchip,synclko-disable:
51    $ref: /schemas/types.yaml#/definitions/flag
52    description:
53      Set if the output SYNCLKO clock should be disabled. Do not mix with
54      microchip,synclko-125.
55
56  microchip,pme-active-high:
57    $ref: /schemas/types.yaml#/definitions/flag
58    description:
59      Indicates if the PME pin polarity is active-high.
60
61  microchip,io-drive-strength-microamp:
62    description:
63      IO Pad Drive Strength
64    enum: [8000, 16000]
65    default: 16000
66
67  microchip,hi-drive-strength-microamp:
68    description:
69      High Speed Drive Strength. Controls drive strength of GMII / RGMII /
70      MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
71    enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
72    default: 24000
73
74  microchip,lo-drive-strength-microamp:
75    description:
76      Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
77      COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
78    enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
79    default: 8000
80
81  interrupts:
82    maxItems: 1
83
84  mdio:
85    $ref: /schemas/net/mdio.yaml#
86    unevaluatedProperties: false
87    properties:
88      mdio-parent-bus:
89        $ref: /schemas/types.yaml#/definitions/phandle
90        description:
91          Phandle pointing to the MDIO bus controller connected to the
92          secondary MDIO interface. This property should be used when
93          the internal MDIO bus is accessed via a secondary MDIO
94          interface rather than the primary management interface.
95
96    patternProperties:
97      "^ethernet-phy@[0-9a-f]$":
98        type: object
99        $ref: /schemas/net/ethernet-phy.yaml#
100        unevaluatedProperties: false
101        description:
102          Integrated PHY node
103
104required:
105  - compatible
106  - reg
107
108if:
109  not:
110    properties:
111      compatible:
112        enum:
113          - microchip,ksz8863
114          - microchip,ksz8873
115then:
116  $ref: dsa.yaml#/$defs/ethernet-ports
117else:
118  patternProperties:
119    "^(ethernet-)?ports$":
120      patternProperties:
121        "^(ethernet-)?port@[0-2]$":
122          $ref: dsa-port.yaml#
123          unevaluatedProperties: false
124          properties:
125            microchip,rmii-clk-internal:
126              $ref: /schemas/types.yaml#/definitions/flag
127              description:
128                When ksz88x3 is acting as clock provier (via REFCLKO) it
129                can select between internal and external RMII reference
130                clock. Internal reference clock means that the clock for
131                the RMII of ksz88x3 is provided by the ksz88x3 internally
132                and the REFCLKI pin is unconnected. For the external
133                reference clock, the clock needs to be fed back to ksz88x3
134                via REFCLKI.
135                If microchip,rmii-clk-internal is set, ksz88x3 will provide
136                rmii reference clock internally, otherwise reference clock
137                should be provided externally.
138          dependencies:
139            microchip,rmii-clk-internal: [ethernet]
140
141unevaluatedProperties: false
142
143examples:
144  - |
145    #include <dt-bindings/gpio/gpio.h>
146
147    // Ethernet switch connected via SPI to the host, CPU port wired to eth0:
148    eth0 {
149        fixed-link {
150            speed = <1000>;
151            full-duplex;
152        };
153    };
154
155    spi {
156        #address-cells = <1>;
157        #size-cells = <0>;
158
159        pinctrl-0 = <&pinctrl_spi_ksz>;
160        cs-gpios = <&pioC 25 0>;
161        id = <1>;
162
163        ksz9477: switch@0 {
164            compatible = "microchip,ksz9477";
165            reg = <0>;
166            reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
167
168            spi-max-frequency = <44000000>;
169
170            ethernet-ports {
171                #address-cells = <1>;
172                #size-cells = <0>;
173                port@0 {
174                    reg = <0>;
175                    label = "lan1";
176                };
177                port@1 {
178                    reg = <1>;
179                    label = "lan2";
180                };
181                port@2 {
182                    reg = <2>;
183                    label = "lan3";
184                };
185                port@3 {
186                    reg = <3>;
187                    label = "lan4";
188                };
189                port@4 {
190                    reg = <4>;
191                    label = "lan5";
192                };
193                port@5 {
194                    reg = <5>;
195                    ethernet = <&eth0>;
196                    phy-mode = "rgmii";
197
198                    fixed-link {
199                        speed = <1000>;
200                        full-duplex;
201                    };
202                };
203            };
204        };
205
206        ksz8565: switch@1 {
207            compatible = "microchip,ksz8565";
208            reg = <1>;
209
210            spi-max-frequency = <44000000>;
211
212            ethernet-ports {
213                #address-cells = <1>;
214                #size-cells = <0>;
215                port@0 {
216                    reg = <0>;
217                    label = "lan1";
218                };
219                port@1 {
220                    reg = <1>;
221                    label = "lan2";
222                };
223                port@2 {
224                    reg = <2>;
225                    label = "lan3";
226                };
227                port@3 {
228                    reg = <3>;
229                    label = "lan4";
230                };
231                port@6 {
232                    reg = <6>;
233                    ethernet = <&eth0>;
234                    phy-mode = "rgmii";
235
236                    fixed-link {
237                        speed = <1000>;
238                        full-duplex;
239                    };
240                };
241            };
242        };
243    };
244...
245