1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT7530 and MT7531 Ethernet Switches 8 9maintainers: 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 - Daniel Golle <daniel@makrotopia.org> 15 16description: | 17 There are three versions of MT7530, standalone, in a multi-chip module and 18 built-into a SoC. 19 20 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 21 MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 22 23 The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four 24 Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's 25 memory map rather than using MDIO. The switch has an internally connected 10G 26 CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs. 27 28 The MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has 10/100 PHYs 29 and the switch registers are directly mapped into SoC's memory map rather than 30 using MDIO. The DSA driver currently doesn't support MT7620 variants. 31 32 There is only the standalone version of MT7531. 33 34 Port 5 on MT7530 supports various configurations: 35 36 - Port 5 can be used as a CPU port. 37 38 - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, 39 the gmac of the SoC which is wired to port 5 can connect to the PHY. 40 This is usually used for connecting the wan port directly to the CPU to 41 achieve 2 Gbps routing in total. 42 43 The driver looks up the reg on the ethernet-phy node, which the phy-handle 44 property on the gmac node refers to, to mux the specified phy. 45 46 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 47 compatible string and the reg must be 1. So, for now, only gmac1 of a 48 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 49 50 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 51 52 Check out example 5. 53 54 - For the multi-chip module MT7530, in case of an external phy wired to 55 gmac1 of the SoC, port 5 must not be enabled. 56 57 In case of muxing PHY 0 or 4, the external phy must not be enabled. 58 59 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60 61 Check out example 6. 62 63 - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port. 64 65 For the multi-chip module MT7530, the external phy must be wired TX to TX 66 to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired 67 this way. 68 69 For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the 70 external phy is connected TX to TX. 71 72 For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 73 74 Check out example 7. 75 76properties: 77 compatible: 78 oneOf: 79 - description: 80 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 81 const: mediatek,mt7530 82 83 - description: 84 Standalone MT7531 85 const: mediatek,mt7531 86 87 - description: 88 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 89 const: mediatek,mt7621 90 91 - description: 92 Built-in switch of the MT7988 SoC 93 const: mediatek,mt7988-switch 94 95 - description: 96 Built-in switch of the Airoha EN7581 SoC 97 const: airoha,en7581-switch 98 99 - description: 100 Built-in switch of the Airoha AN7583 SoC 101 const: airoha,an7583-switch 102 103 reg: 104 maxItems: 1 105 106 core-supply: 107 description: 108 Phandle to the regulator node necessary for the core power. 109 110 "#gpio-cells": 111 const: 2 112 113 gpio-controller: 114 type: boolean 115 description: | 116 If defined, LED controller of the MT7530 switch will run on GPIO mode. 117 118 There are 15 controllable pins. 119 port 0 LED 0..2 as GPIO 0..2 120 port 1 LED 0..2 as GPIO 3..5 121 port 2 LED 0..2 as GPIO 6..8 122 port 3 LED 0..2 as GPIO 9..11 123 port 4 LED 0..2 as GPIO 12..14 124 125 "#interrupt-cells": 126 const: 1 127 128 interrupt-controller: true 129 130 interrupts: 131 maxItems: 1 132 133 io-supply: 134 description: | 135 Phandle to the regulator node necessary for the I/O power. 136 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 137 details for the regulator setup on these boards. 138 139 mediatek,mcm: 140 type: boolean 141 description: 142 Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 143 switch is a part of the multi-chip module. 144 145 reset-gpios: 146 description: | 147 GPIO to reset the switch. Use this if mediatek,mcm is not used. 148 This property is optional because some boards share the reset line with 149 other components which makes it impossible to probe the switch if the 150 reset line is used. 151 maxItems: 1 152 153 reset-names: 154 const: mcm 155 156 resets: 157 description: 158 Phandle pointing to the system reset controller with line index for the 159 ethsys. 160 maxItems: 1 161 162patternProperties: 163 "^(ethernet-)?ports$": 164 type: object 165 additionalProperties: true 166 167 patternProperties: 168 "^(ethernet-)?port@[0-6]$": 169 type: object 170 additionalProperties: true 171 172 properties: 173 reg: 174 description: 175 Port address described must be 5 or 6 for CPU port and from 0 to 5 176 for user ports. 177 178 allOf: 179 - if: 180 required: [ ethernet ] 181 then: 182 properties: 183 reg: 184 enum: 185 - 5 186 - 6 187 188required: 189 - compatible 190 - reg 191 192$defs: 193 mt7530-dsa-port: 194 patternProperties: 195 "^(ethernet-)?ports$": 196 patternProperties: 197 "^(ethernet-)?port@[0-6]$": 198 if: 199 required: [ ethernet ] 200 then: 201 if: 202 properties: 203 reg: 204 const: 5 205 then: 206 properties: 207 phy-mode: 208 enum: 209 - gmii 210 - mii 211 - rgmii 212 else: 213 properties: 214 phy-mode: 215 enum: 216 - rgmii 217 - trgmii 218 219 mt7531-dsa-port: 220 patternProperties: 221 "^(ethernet-)?ports$": 222 patternProperties: 223 "^(ethernet-)?port@[0-6]$": 224 if: 225 required: [ ethernet ] 226 then: 227 if: 228 properties: 229 reg: 230 const: 5 231 then: 232 properties: 233 phy-mode: 234 enum: 235 - 1000base-x 236 - 2500base-x 237 - rgmii 238 - sgmii 239 else: 240 properties: 241 phy-mode: 242 enum: 243 - 1000base-x 244 - 2500base-x 245 - sgmii 246 247allOf: 248 - $ref: dsa.yaml#/$defs/ethernet-ports 249 - if: 250 required: 251 - mediatek,mcm 252 then: 253 properties: 254 reset-gpios: false 255 256 required: 257 - resets 258 - reset-names 259 260 - dependencies: 261 interrupt-controller: [ interrupts ] 262 263 - if: 264 properties: 265 compatible: 266 const: mediatek,mt7530 267 then: 268 $ref: "#/$defs/mt7530-dsa-port" 269 required: 270 - core-supply 271 - io-supply 272 273 - if: 274 properties: 275 compatible: 276 const: mediatek,mt7531 277 then: 278 $ref: "#/$defs/mt7531-dsa-port" 279 properties: 280 gpio-controller: false 281 mediatek,mcm: false 282 283 - if: 284 properties: 285 compatible: 286 const: mediatek,mt7621 287 then: 288 $ref: "#/$defs/mt7530-dsa-port" 289 required: 290 - mediatek,mcm 291 292 - if: 293 properties: 294 compatible: 295 enum: 296 - mediatek,mt7988-switch 297 - airoha,en7581-switch 298 - airoha,an7583-switch 299 then: 300 $ref: "#/$defs/mt7530-dsa-port" 301 properties: 302 gpio-controller: false 303 mediatek,mcm: false 304 reset-names: false 305 306unevaluatedProperties: false 307 308examples: 309 # Example 1: Standalone MT7530 310 - | 311 #include <dt-bindings/gpio/gpio.h> 312 313 mdio { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 switch@1f { 318 compatible = "mediatek,mt7530"; 319 reg = <0x1f>; 320 321 reset-gpios = <&pio 33 0>; 322 323 core-supply = <&mt6323_vpa_reg>; 324 io-supply = <&mt6323_vemc3v3_reg>; 325 326 ethernet-ports { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 330 port@0 { 331 reg = <0>; 332 label = "lan1"; 333 }; 334 335 port@1 { 336 reg = <1>; 337 label = "lan2"; 338 }; 339 340 port@2 { 341 reg = <2>; 342 label = "lan3"; 343 }; 344 345 port@3 { 346 reg = <3>; 347 label = "lan4"; 348 }; 349 350 port@4 { 351 reg = <4>; 352 label = "wan"; 353 }; 354 355 port@6 { 356 reg = <6>; 357 ethernet = <&gmac0>; 358 phy-mode = "rgmii"; 359 360 fixed-link { 361 speed = <1000>; 362 full-duplex; 363 pause; 364 }; 365 }; 366 }; 367 }; 368 }; 369 370 # Example 2: MT7530 in MT7623AI SoC 371 - | 372 #include <dt-bindings/reset/mt2701-resets.h> 373 374 mdio { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 378 switch@1f { 379 compatible = "mediatek,mt7530"; 380 reg = <0x1f>; 381 382 mediatek,mcm; 383 resets = <ðsys MT2701_ETHSYS_MCM_RST>; 384 reset-names = "mcm"; 385 386 core-supply = <&mt6323_vpa_reg>; 387 io-supply = <&mt6323_vemc3v3_reg>; 388 389 ethernet-ports { 390 #address-cells = <1>; 391 #size-cells = <0>; 392 393 port@0 { 394 reg = <0>; 395 label = "lan1"; 396 }; 397 398 port@1 { 399 reg = <1>; 400 label = "lan2"; 401 }; 402 403 port@2 { 404 reg = <2>; 405 label = "lan3"; 406 }; 407 408 port@3 { 409 reg = <3>; 410 label = "lan4"; 411 }; 412 413 port@4 { 414 reg = <4>; 415 label = "wan"; 416 }; 417 418 port@6 { 419 reg = <6>; 420 ethernet = <&gmac0>; 421 phy-mode = "trgmii"; 422 423 fixed-link { 424 speed = <1000>; 425 full-duplex; 426 pause; 427 }; 428 }; 429 }; 430 }; 431 }; 432 433 # Example 3: Standalone MT7531 434 - | 435 #include <dt-bindings/gpio/gpio.h> 436 #include <dt-bindings/interrupt-controller/irq.h> 437 438 mdio { 439 #address-cells = <1>; 440 #size-cells = <0>; 441 442 switch@0 { 443 compatible = "mediatek,mt7531"; 444 reg = <0>; 445 446 reset-gpios = <&pio 54 0>; 447 448 interrupt-controller; 449 #interrupt-cells = <1>; 450 interrupt-parent = <&pio>; 451 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 452 453 ethernet-ports { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 457 port@0 { 458 reg = <0>; 459 label = "lan1"; 460 }; 461 462 port@1 { 463 reg = <1>; 464 label = "lan2"; 465 }; 466 467 port@2 { 468 reg = <2>; 469 label = "lan3"; 470 }; 471 472 port@3 { 473 reg = <3>; 474 label = "lan4"; 475 }; 476 477 port@4 { 478 reg = <4>; 479 label = "wan"; 480 }; 481 482 port@6 { 483 reg = <6>; 484 ethernet = <&gmac0>; 485 phy-mode = "2500base-x"; 486 487 fixed-link { 488 speed = <2500>; 489 full-duplex; 490 pause; 491 }; 492 }; 493 }; 494 }; 495 }; 496 497 # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 498 - | 499 #include <dt-bindings/interrupt-controller/mips-gic.h> 500 #include <dt-bindings/reset/mt7621-reset.h> 501 502 mdio { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 switch@1f { 507 compatible = "mediatek,mt7621"; 508 reg = <0x1f>; 509 510 mediatek,mcm; 511 resets = <&sysc MT7621_RST_MCM>; 512 reset-names = "mcm"; 513 514 interrupt-controller; 515 #interrupt-cells = <1>; 516 interrupt-parent = <&gic>; 517 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 518 519 ethernet-ports { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 port@0 { 524 reg = <0>; 525 label = "lan1"; 526 }; 527 528 port@1 { 529 reg = <1>; 530 label = "lan2"; 531 }; 532 533 port@2 { 534 reg = <2>; 535 label = "lan3"; 536 }; 537 538 port@3 { 539 reg = <3>; 540 label = "lan4"; 541 }; 542 543 port@4 { 544 reg = <4>; 545 label = "wan"; 546 }; 547 548 port@6 { 549 reg = <6>; 550 ethernet = <&gmac0>; 551 phy-mode = "trgmii"; 552 553 fixed-link { 554 speed = <1000>; 555 full-duplex; 556 pause; 557 }; 558 }; 559 }; 560 }; 561 }; 562 563 # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 564 - | 565 #include <dt-bindings/interrupt-controller/mips-gic.h> 566 #include <dt-bindings/reset/mt7621-reset.h> 567 568 ethernet { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 572 pinctrl-names = "default"; 573 pinctrl-0 = <&rgmii2_pins>; 574 575 mac@1 { 576 compatible = "mediatek,eth-mac"; 577 reg = <1>; 578 579 phy-mode = "rgmii"; 580 phy-handle = <&example5_ethphy4>; 581 }; 582 583 mdio { 584 #address-cells = <1>; 585 #size-cells = <0>; 586 587 /* MT7530's phy4 */ 588 example5_ethphy4: ethernet-phy@4 { 589 reg = <4>; 590 }; 591 592 switch@1f { 593 compatible = "mediatek,mt7621"; 594 reg = <0x1f>; 595 596 mediatek,mcm; 597 resets = <&sysc MT7621_RST_MCM>; 598 reset-names = "mcm"; 599 600 interrupt-controller; 601 #interrupt-cells = <1>; 602 interrupt-parent = <&gic>; 603 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 604 605 ethernet-ports { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 609 port@0 { 610 reg = <0>; 611 label = "lan1"; 612 }; 613 614 port@1 { 615 reg = <1>; 616 label = "lan2"; 617 }; 618 619 port@2 { 620 reg = <2>; 621 label = "lan3"; 622 }; 623 624 port@3 { 625 reg = <3>; 626 label = "lan4"; 627 }; 628 629 /* Commented out, phy4 is connected to gmac1. 630 port@4 { 631 reg = <4>; 632 label = "wan"; 633 }; 634 */ 635 636 port@6 { 637 reg = <6>; 638 ethernet = <&gmac0>; 639 phy-mode = "trgmii"; 640 641 fixed-link { 642 speed = <1000>; 643 full-duplex; 644 pause; 645 }; 646 }; 647 }; 648 }; 649 }; 650 }; 651 652 # Example 6: MT7621: mux external phy to SoC's gmac1 653 - | 654 #include <dt-bindings/interrupt-controller/mips-gic.h> 655 #include <dt-bindings/reset/mt7621-reset.h> 656 657 ethernet { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 661 pinctrl-names = "default"; 662 pinctrl-0 = <&rgmii2_pins>; 663 664 mac@1 { 665 compatible = "mediatek,eth-mac"; 666 reg = <1>; 667 668 phy-mode = "rgmii"; 669 phy-handle = <&example6_ethphy7>; 670 }; 671 672 mdio { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 676 /* External PHY */ 677 example6_ethphy7: ethernet-phy@7 { 678 reg = <7>; 679 phy-mode = "rgmii"; 680 }; 681 682 switch@1f { 683 compatible = "mediatek,mt7621"; 684 reg = <0x1f>; 685 686 mediatek,mcm; 687 resets = <&sysc MT7621_RST_MCM>; 688 reset-names = "mcm"; 689 690 interrupt-controller; 691 #interrupt-cells = <1>; 692 interrupt-parent = <&gic>; 693 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 694 695 ethernet-ports { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 port@0 { 700 reg = <0>; 701 label = "lan1"; 702 }; 703 704 port@1 { 705 reg = <1>; 706 label = "lan2"; 707 }; 708 709 port@2 { 710 reg = <2>; 711 label = "lan3"; 712 }; 713 714 port@3 { 715 reg = <3>; 716 label = "lan4"; 717 }; 718 719 port@4 { 720 reg = <4>; 721 label = "wan"; 722 }; 723 724 port@6 { 725 reg = <6>; 726 ethernet = <&gmac0>; 727 phy-mode = "trgmii"; 728 729 fixed-link { 730 speed = <1000>; 731 full-duplex; 732 pause; 733 }; 734 }; 735 }; 736 }; 737 }; 738 }; 739 740 # Example 7: MT7621: mux external phy to MT7530's port 5 741 - | 742 #include <dt-bindings/interrupt-controller/mips-gic.h> 743 #include <dt-bindings/reset/mt7621-reset.h> 744 745 ethernet { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 749 pinctrl-names = "default"; 750 pinctrl-0 = <&rgmii2_pins>; 751 752 mdio { 753 #address-cells = <1>; 754 #size-cells = <0>; 755 756 /* External PHY */ 757 example7_ethphy7: ethernet-phy@7 { 758 reg = <7>; 759 phy-mode = "rgmii"; 760 }; 761 762 switch@1f { 763 compatible = "mediatek,mt7621"; 764 reg = <0x1f>; 765 766 mediatek,mcm; 767 resets = <&sysc MT7621_RST_MCM>; 768 reset-names = "mcm"; 769 770 interrupt-controller; 771 #interrupt-cells = <1>; 772 interrupt-parent = <&gic>; 773 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 774 775 ethernet-ports { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 779 port@0 { 780 reg = <0>; 781 label = "lan1"; 782 }; 783 784 port@1 { 785 reg = <1>; 786 label = "lan2"; 787 }; 788 789 port@2 { 790 reg = <2>; 791 label = "lan3"; 792 }; 793 794 port@3 { 795 reg = <3>; 796 label = "lan4"; 797 }; 798 799 port@4 { 800 reg = <4>; 801 label = "wan"; 802 }; 803 804 port@5 { 805 reg = <5>; 806 label = "extphy"; 807 phy-mode = "rgmii-txid"; 808 phy-handle = <&example7_ethphy7>; 809 }; 810 811 port@6 { 812 reg = <6>; 813 ethernet = <&gmac0>; 814 phy-mode = "trgmii"; 815 816 fixed-link { 817 speed = <1000>; 818 full-duplex; 819 pause; 820 }; 821 }; 822 }; 823 }; 824 }; 825 }; 826