1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT7530 and MT7531 Ethernet Switches 8 9maintainers: 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 15description: | 16 There are two versions of MT7530, standalone and in a multi-chip module. 17 18 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 19 MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 20 21 MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs 22 and the switch registers are directly mapped into SoC's memory map rather than 23 using MDIO. The DSA driver currently doesn't support this. 24 25 There is only the standalone version of MT7531. 26 27 Port 5 on MT7530 has got various ways of configuration. 28 29 For standalone MT7530: 30 31 - Port 5 can be used as a CPU port. 32 33 - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC 34 which port 5 is wired to. Usually used for connecting the wan port 35 directly to the CPU to achieve 2 Gbps routing in total. 36 37 The driver looks up the reg on the ethernet-phy node which the phy-handle 38 property refers to on the gmac node to mux the specified phy. 39 40 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 41 compatible string and the reg must be 1. So, for now, only gmac1 of an 42 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 43 Check out example 5 for a similar configuration. 44 45 - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. 46 Check out example 7 for a similar configuration. 47 48 For multi-chip module MT7530: 49 50 - Port 5 can be used as a CPU port. 51 52 - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. 53 Usually used for connecting the wan port directly to the CPU to achieve 2 54 Gbps routing in total. 55 56 The driver looks up the reg on the ethernet-phy node which the phy-handle 57 property refers to on the gmac node to mux the specified phy. 58 59 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60 Check out example 5. 61 62 - In case of an external phy wired to gmac1 of the SoC, port 5 must not be 63 enabled. 64 65 In case of muxing PHY 0 or 4, the external phy must not be enabled. 66 67 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 68 Check out example 6. 69 70 - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. 71 The external phy must be wired TX to TX to gmac1 of the SoC for this to 72 work. Ubiquiti EdgeRouter X SFP is wired this way. 73 74 Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. 75 76 For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 77 Check out example 7. 78 79properties: 80 compatible: 81 oneOf: 82 - description: 83 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 84 const: mediatek,mt7530 85 86 - description: 87 Standalone MT7531 88 const: mediatek,mt7531 89 90 - description: 91 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 92 const: mediatek,mt7621 93 94 reg: 95 maxItems: 1 96 97 core-supply: 98 description: 99 Phandle to the regulator node necessary for the core power. 100 101 "#gpio-cells": 102 const: 2 103 104 gpio-controller: 105 type: boolean 106 description: 107 If defined, LED controller of the MT7530 switch will run on GPIO mode. 108 109 There are 15 controllable pins. 110 port 0 LED 0..2 as GPIO 0..2 111 port 1 LED 0..2 as GPIO 3..5 112 port 2 LED 0..2 as GPIO 6..8 113 port 3 LED 0..2 as GPIO 9..11 114 port 4 LED 0..2 as GPIO 12..14 115 116 "#interrupt-cells": 117 const: 1 118 119 interrupt-controller: true 120 121 interrupts: 122 maxItems: 1 123 124 io-supply: 125 description: 126 Phandle to the regulator node necessary for the I/O power. 127 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 128 details for the regulator setup on these boards. 129 130 mediatek,mcm: 131 type: boolean 132 description: 133 Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 134 switch is a part of the multi-chip module. 135 136 reset-gpios: 137 description: 138 GPIO to reset the switch. Use this if mediatek,mcm is not used. 139 This property is optional because some boards share the reset line with 140 other components which makes it impossible to probe the switch if the 141 reset line is used. 142 maxItems: 1 143 144 reset-names: 145 const: mcm 146 147 resets: 148 description: 149 Phandle pointing to the system reset controller with line index for the 150 ethsys. 151 maxItems: 1 152 153patternProperties: 154 "^(ethernet-)?ports$": 155 type: object 156 157 patternProperties: 158 "^(ethernet-)?port@[0-9]+$": 159 type: object 160 description: Ethernet switch ports 161 162 unevaluatedProperties: false 163 164 properties: 165 reg: 166 description: 167 Port address described must be 5 or 6 for CPU port and from 0 to 5 168 for user ports. 169 170 allOf: 171 - $ref: dsa-port.yaml# 172 - if: 173 required: [ ethernet ] 174 then: 175 properties: 176 reg: 177 enum: 178 - 5 179 - 6 180 181required: 182 - compatible 183 - reg 184 185$defs: 186 mt7530-dsa-port: 187 patternProperties: 188 "^(ethernet-)?ports$": 189 patternProperties: 190 "^(ethernet-)?port@[0-9]+$": 191 if: 192 required: [ ethernet ] 193 then: 194 if: 195 properties: 196 reg: 197 const: 5 198 then: 199 properties: 200 phy-mode: 201 enum: 202 - gmii 203 - mii 204 - rgmii 205 else: 206 properties: 207 phy-mode: 208 enum: 209 - rgmii 210 - trgmii 211 212 mt7531-dsa-port: 213 patternProperties: 214 "^(ethernet-)?ports$": 215 patternProperties: 216 "^(ethernet-)?port@[0-9]+$": 217 if: 218 required: [ ethernet ] 219 then: 220 if: 221 properties: 222 reg: 223 const: 5 224 then: 225 properties: 226 phy-mode: 227 enum: 228 - 1000base-x 229 - 2500base-x 230 - rgmii 231 - sgmii 232 else: 233 properties: 234 phy-mode: 235 enum: 236 - 1000base-x 237 - 2500base-x 238 - sgmii 239 240allOf: 241 - $ref: dsa.yaml# 242 - if: 243 required: 244 - mediatek,mcm 245 then: 246 properties: 247 reset-gpios: false 248 249 required: 250 - resets 251 - reset-names 252 253 - dependencies: 254 interrupt-controller: [ interrupts ] 255 256 - if: 257 properties: 258 compatible: 259 const: mediatek,mt7530 260 then: 261 $ref: "#/$defs/mt7530-dsa-port" 262 required: 263 - core-supply 264 - io-supply 265 266 - if: 267 properties: 268 compatible: 269 const: mediatek,mt7531 270 then: 271 $ref: "#/$defs/mt7531-dsa-port" 272 properties: 273 gpio-controller: false 274 mediatek,mcm: false 275 276 - if: 277 properties: 278 compatible: 279 const: mediatek,mt7621 280 then: 281 $ref: "#/$defs/mt7530-dsa-port" 282 required: 283 - mediatek,mcm 284 285unevaluatedProperties: false 286 287examples: 288 # Example 1: Standalone MT7530 289 - | 290 #include <dt-bindings/gpio/gpio.h> 291 292 mdio { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 296 switch@1f { 297 compatible = "mediatek,mt7530"; 298 reg = <0x1f>; 299 300 reset-gpios = <&pio 33 0>; 301 302 core-supply = <&mt6323_vpa_reg>; 303 io-supply = <&mt6323_vemc3v3_reg>; 304 305 ethernet-ports { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 309 port@0 { 310 reg = <0>; 311 label = "lan1"; 312 }; 313 314 port@1 { 315 reg = <1>; 316 label = "lan2"; 317 }; 318 319 port@2 { 320 reg = <2>; 321 label = "lan3"; 322 }; 323 324 port@3 { 325 reg = <3>; 326 label = "lan4"; 327 }; 328 329 port@4 { 330 reg = <4>; 331 label = "wan"; 332 }; 333 334 port@6 { 335 reg = <6>; 336 ethernet = <&gmac0>; 337 phy-mode = "rgmii"; 338 339 fixed-link { 340 speed = <1000>; 341 full-duplex; 342 pause; 343 }; 344 }; 345 }; 346 }; 347 }; 348 349 # Example 2: MT7530 in MT7623AI SoC 350 - | 351 #include <dt-bindings/reset/mt2701-resets.h> 352 353 mdio { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 357 switch@1f { 358 compatible = "mediatek,mt7530"; 359 reg = <0x1f>; 360 361 mediatek,mcm; 362 resets = <ðsys MT2701_ETHSYS_MCM_RST>; 363 reset-names = "mcm"; 364 365 core-supply = <&mt6323_vpa_reg>; 366 io-supply = <&mt6323_vemc3v3_reg>; 367 368 ethernet-ports { 369 #address-cells = <1>; 370 #size-cells = <0>; 371 372 port@0 { 373 reg = <0>; 374 label = "lan1"; 375 }; 376 377 port@1 { 378 reg = <1>; 379 label = "lan2"; 380 }; 381 382 port@2 { 383 reg = <2>; 384 label = "lan3"; 385 }; 386 387 port@3 { 388 reg = <3>; 389 label = "lan4"; 390 }; 391 392 port@4 { 393 reg = <4>; 394 label = "wan"; 395 }; 396 397 port@6 { 398 reg = <6>; 399 ethernet = <&gmac0>; 400 phy-mode = "trgmii"; 401 402 fixed-link { 403 speed = <1000>; 404 full-duplex; 405 pause; 406 }; 407 }; 408 }; 409 }; 410 }; 411 412 # Example 3: Standalone MT7531 413 - | 414 #include <dt-bindings/gpio/gpio.h> 415 #include <dt-bindings/interrupt-controller/irq.h> 416 417 mdio { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 421 switch@0 { 422 compatible = "mediatek,mt7531"; 423 reg = <0>; 424 425 reset-gpios = <&pio 54 0>; 426 427 interrupt-controller; 428 #interrupt-cells = <1>; 429 interrupt-parent = <&pio>; 430 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 431 432 ethernet-ports { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 port@0 { 437 reg = <0>; 438 label = "lan1"; 439 }; 440 441 port@1 { 442 reg = <1>; 443 label = "lan2"; 444 }; 445 446 port@2 { 447 reg = <2>; 448 label = "lan3"; 449 }; 450 451 port@3 { 452 reg = <3>; 453 label = "lan4"; 454 }; 455 456 port@4 { 457 reg = <4>; 458 label = "wan"; 459 }; 460 461 port@6 { 462 reg = <6>; 463 ethernet = <&gmac0>; 464 phy-mode = "2500base-x"; 465 466 fixed-link { 467 speed = <2500>; 468 full-duplex; 469 pause; 470 }; 471 }; 472 }; 473 }; 474 }; 475 476 # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 477 - | 478 #include <dt-bindings/interrupt-controller/mips-gic.h> 479 #include <dt-bindings/reset/mt7621-reset.h> 480 481 mdio { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 switch@1f { 486 compatible = "mediatek,mt7621"; 487 reg = <0x1f>; 488 489 mediatek,mcm; 490 resets = <&sysc MT7621_RST_MCM>; 491 reset-names = "mcm"; 492 493 interrupt-controller; 494 #interrupt-cells = <1>; 495 interrupt-parent = <&gic>; 496 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 497 498 ethernet-ports { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 502 port@0 { 503 reg = <0>; 504 label = "lan1"; 505 }; 506 507 port@1 { 508 reg = <1>; 509 label = "lan2"; 510 }; 511 512 port@2 { 513 reg = <2>; 514 label = "lan3"; 515 }; 516 517 port@3 { 518 reg = <3>; 519 label = "lan4"; 520 }; 521 522 port@4 { 523 reg = <4>; 524 label = "wan"; 525 }; 526 527 port@6 { 528 reg = <6>; 529 ethernet = <&gmac0>; 530 phy-mode = "trgmii"; 531 532 fixed-link { 533 speed = <1000>; 534 full-duplex; 535 pause; 536 }; 537 }; 538 }; 539 }; 540 }; 541 542 # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 543 - | 544 #include <dt-bindings/interrupt-controller/mips-gic.h> 545 #include <dt-bindings/reset/mt7621-reset.h> 546 547 ethernet { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 551 pinctrl-names = "default"; 552 pinctrl-0 = <&rgmii2_pins>; 553 554 mac@1 { 555 compatible = "mediatek,eth-mac"; 556 reg = <1>; 557 558 phy-mode = "rgmii"; 559 phy-handle = <&example5_ethphy4>; 560 }; 561 562 mdio { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 /* MT7530's phy4 */ 567 example5_ethphy4: ethernet-phy@4 { 568 reg = <4>; 569 }; 570 571 switch@1f { 572 compatible = "mediatek,mt7621"; 573 reg = <0x1f>; 574 575 mediatek,mcm; 576 resets = <&sysc MT7621_RST_MCM>; 577 reset-names = "mcm"; 578 579 interrupt-controller; 580 #interrupt-cells = <1>; 581 interrupt-parent = <&gic>; 582 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 583 584 ethernet-ports { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 588 port@0 { 589 reg = <0>; 590 label = "lan1"; 591 }; 592 593 port@1 { 594 reg = <1>; 595 label = "lan2"; 596 }; 597 598 port@2 { 599 reg = <2>; 600 label = "lan3"; 601 }; 602 603 port@3 { 604 reg = <3>; 605 label = "lan4"; 606 }; 607 608 /* Commented out, phy4 is muxed to gmac1. 609 port@4 { 610 reg = <4>; 611 label = "wan"; 612 }; 613 */ 614 615 port@6 { 616 reg = <6>; 617 ethernet = <&gmac0>; 618 phy-mode = "trgmii"; 619 620 fixed-link { 621 speed = <1000>; 622 full-duplex; 623 pause; 624 }; 625 }; 626 }; 627 }; 628 }; 629 }; 630 631 # Example 6: MT7621: mux external phy to SoC's gmac1 632 - | 633 #include <dt-bindings/interrupt-controller/mips-gic.h> 634 #include <dt-bindings/reset/mt7621-reset.h> 635 636 ethernet { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 640 pinctrl-names = "default"; 641 pinctrl-0 = <&rgmii2_pins>; 642 643 mac@1 { 644 compatible = "mediatek,eth-mac"; 645 reg = <1>; 646 647 phy-mode = "rgmii"; 648 phy-handle = <&example6_ethphy7>; 649 }; 650 651 mdio { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 655 /* External PHY */ 656 example6_ethphy7: ethernet-phy@7 { 657 reg = <7>; 658 phy-mode = "rgmii"; 659 }; 660 661 switch@1f { 662 compatible = "mediatek,mt7621"; 663 reg = <0x1f>; 664 665 mediatek,mcm; 666 resets = <&sysc MT7621_RST_MCM>; 667 reset-names = "mcm"; 668 669 interrupt-controller; 670 #interrupt-cells = <1>; 671 interrupt-parent = <&gic>; 672 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 673 674 ethernet-ports { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 678 port@0 { 679 reg = <0>; 680 label = "lan1"; 681 }; 682 683 port@1 { 684 reg = <1>; 685 label = "lan2"; 686 }; 687 688 port@2 { 689 reg = <2>; 690 label = "lan3"; 691 }; 692 693 port@3 { 694 reg = <3>; 695 label = "lan4"; 696 }; 697 698 port@4 { 699 reg = <4>; 700 label = "wan"; 701 }; 702 703 port@6 { 704 reg = <6>; 705 ethernet = <&gmac0>; 706 phy-mode = "trgmii"; 707 708 fixed-link { 709 speed = <1000>; 710 full-duplex; 711 pause; 712 }; 713 }; 714 }; 715 }; 716 }; 717 }; 718 719 # Example 7: MT7621: mux external phy to MT7530's port 5 720 - | 721 #include <dt-bindings/interrupt-controller/mips-gic.h> 722 #include <dt-bindings/reset/mt7621-reset.h> 723 724 ethernet { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 728 pinctrl-names = "default"; 729 pinctrl-0 = <&rgmii2_pins>; 730 731 mdio { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 735 /* External PHY */ 736 example7_ethphy7: ethernet-phy@7 { 737 reg = <7>; 738 phy-mode = "rgmii"; 739 }; 740 741 switch@1f { 742 compatible = "mediatek,mt7621"; 743 reg = <0x1f>; 744 745 mediatek,mcm; 746 resets = <&sysc MT7621_RST_MCM>; 747 reset-names = "mcm"; 748 749 interrupt-controller; 750 #interrupt-cells = <1>; 751 interrupt-parent = <&gic>; 752 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 753 754 ethernet-ports { 755 #address-cells = <1>; 756 #size-cells = <0>; 757 758 port@0 { 759 reg = <0>; 760 label = "lan1"; 761 }; 762 763 port@1 { 764 reg = <1>; 765 label = "lan2"; 766 }; 767 768 port@2 { 769 reg = <2>; 770 label = "lan3"; 771 }; 772 773 port@3 { 774 reg = <3>; 775 label = "lan4"; 776 }; 777 778 port@4 { 779 reg = <4>; 780 label = "wan"; 781 }; 782 783 port@5 { 784 reg = <5>; 785 label = "extphy"; 786 phy-mode = "rgmii-txid"; 787 phy-handle = <&example7_ethphy7>; 788 }; 789 790 port@6 { 791 reg = <6>; 792 ethernet = <&gmac0>; 793 phy-mode = "trgmii"; 794 795 fixed-link { 796 speed = <1000>; 797 full-duplex; 798 pause; 799 }; 800 }; 801 }; 802 }; 803 }; 804 }; 805