1e0dda311SFrank Wunderlich# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2e0dda311SFrank Wunderlich%YAML 1.2 3e0dda311SFrank Wunderlich--- 4e0dda311SFrank Wunderlich$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5e0dda311SFrank Wunderlich$schema: http://devicetree.org/meta-schemas/core.yaml# 6e0dda311SFrank Wunderlich 7214537cdSArınç ÜNALtitle: Mediatek MT7530 and MT7531 Ethernet Switches 8e0dda311SFrank Wunderlich 9e0dda311SFrank Wunderlichmaintainers: 10214537cdSArınç ÜNAL - Arınç ÜNAL <arinc.unal@arinc9.com> 11e0dda311SFrank Wunderlich - Landen Chao <Landen.Chao@mediatek.com> 12e0dda311SFrank Wunderlich - DENG Qingfang <dqfext@gmail.com> 13214537cdSArınç ÜNAL - Sean Wang <sean.wang@mediatek.com> 14386f5fc9SDaniel Golle - Daniel Golle <daniel@makrotopia.org> 15e0dda311SFrank Wunderlich 16e0dda311SFrank Wunderlichdescription: | 17386f5fc9SDaniel Golle There are three versions of MT7530, standalone, in a multi-chip module and 18386f5fc9SDaniel Golle built-into a SoC. 19e0dda311SFrank Wunderlich 20cd7e2b97SArınç ÜNAL MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 21cd7e2b97SArınç ÜNAL MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 22e0dda311SFrank Wunderlich 23386f5fc9SDaniel Golle The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four 24386f5fc9SDaniel Golle Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's 25c0c68e4dSChris Packham memory map rather than using MDIO. The switch has an internally connected 10G 26386f5fc9SDaniel Golle CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs. 27386f5fc9SDaniel Golle 28c0c68e4dSChris Packham The MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has 10/100 PHYs 29cd7e2b97SArınç ÜNAL and the switch registers are directly mapped into SoC's memory map rather than 30386f5fc9SDaniel Golle using MDIO. The DSA driver currently doesn't support MT7620 variants. 31e0dda311SFrank Wunderlich 32cd7e2b97SArınç ÜNAL There is only the standalone version of MT7531. 33e0dda311SFrank Wunderlich 34c0c68e4dSChris Packham Port 5 on MT7530 supports various configurations: 35cd7e2b97SArınç ÜNAL 36cd7e2b97SArınç ÜNAL - Port 5 can be used as a CPU port. 37cd7e2b97SArınç ÜNAL 38a71fad0fSArınç ÜNAL - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, 39a71fad0fSArınç ÜNAL the gmac of the SoC which is wired to port 5 can connect to the PHY. 40a71fad0fSArınç ÜNAL This is usually used for connecting the wan port directly to the CPU to 41a71fad0fSArınç ÜNAL achieve 2 Gbps routing in total. 42cd7e2b97SArınç ÜNAL 43a71fad0fSArınç ÜNAL The driver looks up the reg on the ethernet-phy node, which the phy-handle 44a71fad0fSArınç ÜNAL property on the gmac node refers to, to mux the specified phy. 45cd7e2b97SArınç ÜNAL 46cd7e2b97SArınç ÜNAL The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 47a71fad0fSArınç ÜNAL compatible string and the reg must be 1. So, for now, only gmac1 of a 48cd7e2b97SArınç ÜNAL MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 49cd7e2b97SArınç ÜNAL 50cd7e2b97SArınç ÜNAL For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 51a71fad0fSArınç ÜNAL 52cd7e2b97SArınç ÜNAL Check out example 5. 53cd7e2b97SArınç ÜNAL 54a71fad0fSArınç ÜNAL - For the multi-chip module MT7530, in case of an external phy wired to 55a71fad0fSArınç ÜNAL gmac1 of the SoC, port 5 must not be enabled. 56cd7e2b97SArınç ÜNAL 57cd7e2b97SArınç ÜNAL In case of muxing PHY 0 or 4, the external phy must not be enabled. 58cd7e2b97SArınç ÜNAL 59cd7e2b97SArınç ÜNAL For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60a71fad0fSArınç ÜNAL 61cd7e2b97SArınç ÜNAL Check out example 6. 62cd7e2b97SArınç ÜNAL 636ca80638SFlorian Fainelli - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port. 64cd7e2b97SArınç ÜNAL 65a71fad0fSArınç ÜNAL For the multi-chip module MT7530, the external phy must be wired TX to TX 66a71fad0fSArınç ÜNAL to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired 67a71fad0fSArınç ÜNAL this way. 68a71fad0fSArınç ÜNAL 69a71fad0fSArınç ÜNAL For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the 70a71fad0fSArınç ÜNAL external phy is connected TX to TX. 71cd7e2b97SArınç ÜNAL 72cd7e2b97SArınç ÜNAL For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 73a71fad0fSArınç ÜNAL 74cd7e2b97SArınç ÜNAL Check out example 7. 75e0dda311SFrank Wunderlich 76e0dda311SFrank Wunderlichproperties: 77e0dda311SFrank Wunderlich compatible: 78214537cdSArınç ÜNAL oneOf: 79214537cdSArınç ÜNAL - description: 80214537cdSArınç ÜNAL Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 81214537cdSArınç ÜNAL const: mediatek,mt7530 82214537cdSArınç ÜNAL 83214537cdSArınç ÜNAL - description: 84214537cdSArınç ÜNAL Standalone MT7531 85214537cdSArınç ÜNAL const: mediatek,mt7531 86214537cdSArınç ÜNAL 87214537cdSArınç ÜNAL - description: 88214537cdSArınç ÜNAL Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 89214537cdSArınç ÜNAL const: mediatek,mt7621 90e0dda311SFrank Wunderlich 91386f5fc9SDaniel Golle - description: 92386f5fc9SDaniel Golle Built-in switch of the MT7988 SoC 93386f5fc9SDaniel Golle const: mediatek,mt7988-switch 94386f5fc9SDaniel Golle 95101a002aSLorenzo Bianconi - description: 96101a002aSLorenzo Bianconi Built-in switch of the Airoha EN7581 SoC 97101a002aSLorenzo Bianconi const: airoha,en7581-switch 98101a002aSLorenzo Bianconi 99fef18488SChristian Marangi - description: 100fef18488SChristian Marangi Built-in switch of the Airoha AN7583 SoC 101fef18488SChristian Marangi const: airoha,an7583-switch 102fef18488SChristian Marangi 1033359619aSRob Herring reg: 1043359619aSRob Herring maxItems: 1 1053359619aSRob Herring 106e0dda311SFrank Wunderlich core-supply: 107e0dda311SFrank Wunderlich description: 108e0dda311SFrank Wunderlich Phandle to the regulator node necessary for the core power. 109e0dda311SFrank Wunderlich 110e0dda311SFrank Wunderlich "#gpio-cells": 111e0dda311SFrank Wunderlich const: 2 112e0dda311SFrank Wunderlich 113e0dda311SFrank Wunderlich gpio-controller: 114e0dda311SFrank Wunderlich type: boolean 1157d8c4891SArınç ÜNAL description: | 1160fbca84eSArınç ÜNAL If defined, LED controller of the MT7530 switch will run on GPIO mode. 1170fbca84eSArınç ÜNAL 1180fbca84eSArınç ÜNAL There are 15 controllable pins. 1190fbca84eSArınç ÜNAL port 0 LED 0..2 as GPIO 0..2 1200fbca84eSArınç ÜNAL port 1 LED 0..2 as GPIO 3..5 1210fbca84eSArınç ÜNAL port 2 LED 0..2 as GPIO 6..8 1220fbca84eSArınç ÜNAL port 3 LED 0..2 as GPIO 9..11 1230fbca84eSArınç ÜNAL port 4 LED 0..2 as GPIO 12..14 124e0dda311SFrank Wunderlich 125e0dda311SFrank Wunderlich "#interrupt-cells": 126e0dda311SFrank Wunderlich const: 1 127e0dda311SFrank Wunderlich 128e0dda311SFrank Wunderlich interrupt-controller: true 129e0dda311SFrank Wunderlich 130e0dda311SFrank Wunderlich interrupts: 131e0dda311SFrank Wunderlich maxItems: 1 132e0dda311SFrank Wunderlich 133e0dda311SFrank Wunderlich io-supply: 1347d8c4891SArınç ÜNAL description: | 135e0dda311SFrank Wunderlich Phandle to the regulator node necessary for the I/O power. 136214537cdSArınç ÜNAL See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 137214537cdSArınç ÜNAL details for the regulator setup on these boards. 138e0dda311SFrank Wunderlich 139*66a44adfSFrank Wunderlich mdio: 140*66a44adfSFrank Wunderlich $ref: /schemas/net/mdio.yaml# 141*66a44adfSFrank Wunderlich unevaluatedProperties: false 142*66a44adfSFrank Wunderlich 143*66a44adfSFrank Wunderlich properties: 144*66a44adfSFrank Wunderlich mediatek,pio: 145*66a44adfSFrank Wunderlich $ref: /schemas/types.yaml#/definitions/phandle 146*66a44adfSFrank Wunderlich description: 147*66a44adfSFrank Wunderlich Phandle pointing to the mediatek pinctrl node. 148*66a44adfSFrank Wunderlich 149e0dda311SFrank Wunderlich mediatek,mcm: 150e0dda311SFrank Wunderlich type: boolean 151e0dda311SFrank Wunderlich description: 152ba9476f7SArınç ÜNAL Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 153ba9476f7SArınç ÜNAL switch is a part of the multi-chip module. 154e0dda311SFrank Wunderlich 155e0dda311SFrank Wunderlich reset-gpios: 1567d8c4891SArınç ÜNAL description: | 157f565c54eSArınç ÜNAL GPIO to reset the switch. Use this if mediatek,mcm is not used. 158f565c54eSArınç ÜNAL This property is optional because some boards share the reset line with 159f565c54eSArınç ÜNAL other components which makes it impossible to probe the switch if the 160f565c54eSArınç ÜNAL reset line is used. 161e0dda311SFrank Wunderlich maxItems: 1 162e0dda311SFrank Wunderlich 163e0dda311SFrank Wunderlich reset-names: 164e0dda311SFrank Wunderlich const: mcm 165e0dda311SFrank Wunderlich 166e0dda311SFrank Wunderlich resets: 167e0dda311SFrank Wunderlich description: 168214537cdSArınç ÜNAL Phandle pointing to the system reset controller with line index for the 169214537cdSArınç ÜNAL ethsys. 170e0dda311SFrank Wunderlich maxItems: 1 171e0dda311SFrank Wunderlich 172e0dda311SFrank WunderlichpatternProperties: 173e0dda311SFrank Wunderlich "^(ethernet-)?ports$": 174e0dda311SFrank Wunderlich type: object 175659fd097SRob Herring additionalProperties: true 176e0dda311SFrank Wunderlich 177e0dda311SFrank Wunderlich patternProperties: 17851ff5150SRob Herring "^(ethernet-)?port@[0-6]$": 179e0dda311SFrank Wunderlich type: object 180659fd097SRob Herring additionalProperties: true 181e0dda311SFrank Wunderlich 182e0dda311SFrank Wunderlich properties: 183e0dda311SFrank Wunderlich reg: 184e0dda311SFrank Wunderlich description: 185214537cdSArınç ÜNAL Port address described must be 5 or 6 for CPU port and from 0 to 5 186214537cdSArınç ÜNAL for user ports. 187e0dda311SFrank Wunderlich 188e0dda311SFrank Wunderlich allOf: 189e0dda311SFrank Wunderlich - if: 1903f301a28SVladimir Oltean required: [ ethernet ] 191e0dda311SFrank Wunderlich then: 192214537cdSArınç ÜNAL properties: 193214537cdSArınç ÜNAL reg: 194214537cdSArınç ÜNAL enum: 195214537cdSArınç ÜNAL - 5 196214537cdSArınç ÜNAL - 6 197214537cdSArınç ÜNAL 198e0dda311SFrank Wunderlichrequired: 199e0dda311SFrank Wunderlich - compatible 200e0dda311SFrank Wunderlich - reg 201e0dda311SFrank Wunderlich 20279a16c3bSArınç ÜNAL$defs: 203588cb646SFrank Wunderlich builtin-dsa-port: 204588cb646SFrank Wunderlich patternProperties: 205588cb646SFrank Wunderlich "^(ethernet-)?ports$": 206588cb646SFrank Wunderlich patternProperties: 207588cb646SFrank Wunderlich "^(ethernet-)?port@[0-6]$": 208588cb646SFrank Wunderlich if: 209588cb646SFrank Wunderlich required: [ ethernet ] 210588cb646SFrank Wunderlich then: 211588cb646SFrank Wunderlich properties: 212588cb646SFrank Wunderlich phy-mode: 213588cb646SFrank Wunderlich const: internal 214588cb646SFrank Wunderlich 21579a16c3bSArınç ÜNAL mt7530-dsa-port: 21679a16c3bSArınç ÜNAL patternProperties: 21779a16c3bSArınç ÜNAL "^(ethernet-)?ports$": 21879a16c3bSArınç ÜNAL patternProperties: 21951ff5150SRob Herring "^(ethernet-)?port@[0-6]$": 22079a16c3bSArınç ÜNAL if: 2213f301a28SVladimir Oltean required: [ ethernet ] 22279a16c3bSArınç ÜNAL then: 22379a16c3bSArınç ÜNAL if: 22479a16c3bSArınç ÜNAL properties: 22579a16c3bSArınç ÜNAL reg: 22679a16c3bSArınç ÜNAL const: 5 22779a16c3bSArınç ÜNAL then: 22879a16c3bSArınç ÜNAL properties: 22979a16c3bSArınç ÜNAL phy-mode: 23079a16c3bSArınç ÜNAL enum: 23179a16c3bSArınç ÜNAL - gmii 23279a16c3bSArınç ÜNAL - mii 23379a16c3bSArınç ÜNAL - rgmii 23479a16c3bSArınç ÜNAL else: 23579a16c3bSArınç ÜNAL properties: 23679a16c3bSArınç ÜNAL phy-mode: 23779a16c3bSArınç ÜNAL enum: 23879a16c3bSArınç ÜNAL - rgmii 23979a16c3bSArınç ÜNAL - trgmii 24079a16c3bSArınç ÜNAL 24179a16c3bSArınç ÜNAL mt7531-dsa-port: 24279a16c3bSArınç ÜNAL patternProperties: 24379a16c3bSArınç ÜNAL "^(ethernet-)?ports$": 24479a16c3bSArınç ÜNAL patternProperties: 24551ff5150SRob Herring "^(ethernet-)?port@[0-6]$": 24679a16c3bSArınç ÜNAL if: 2473f301a28SVladimir Oltean required: [ ethernet ] 24879a16c3bSArınç ÜNAL then: 24979a16c3bSArınç ÜNAL if: 25079a16c3bSArınç ÜNAL properties: 25179a16c3bSArınç ÜNAL reg: 25279a16c3bSArınç ÜNAL const: 5 25379a16c3bSArınç ÜNAL then: 25479a16c3bSArınç ÜNAL properties: 25579a16c3bSArınç ÜNAL phy-mode: 25679a16c3bSArınç ÜNAL enum: 25779a16c3bSArınç ÜNAL - 1000base-x 25879a16c3bSArınç ÜNAL - 2500base-x 25979a16c3bSArınç ÜNAL - rgmii 26079a16c3bSArınç ÜNAL - sgmii 26179a16c3bSArınç ÜNAL else: 26279a16c3bSArınç ÜNAL properties: 26379a16c3bSArınç ÜNAL phy-mode: 26479a16c3bSArınç ÜNAL enum: 26579a16c3bSArınç ÜNAL - 1000base-x 26679a16c3bSArınç ÜNAL - 2500base-x 26779a16c3bSArınç ÜNAL - sgmii 26879a16c3bSArınç ÜNAL 269e0dda311SFrank WunderlichallOf: 2703cec368aSColin Foster - $ref: dsa.yaml#/$defs/ethernet-ports 271e0dda311SFrank Wunderlich - if: 272e0dda311SFrank Wunderlich required: 273e0dda311SFrank Wunderlich - mediatek,mcm 274e0dda311SFrank Wunderlich then: 275f565c54eSArınç ÜNAL properties: 276f565c54eSArınç ÜNAL reset-gpios: false 277f565c54eSArınç ÜNAL 278e0dda311SFrank Wunderlich required: 279e0dda311SFrank Wunderlich - resets 280e0dda311SFrank Wunderlich - reset-names 281e0dda311SFrank Wunderlich 282e0dda311SFrank Wunderlich - dependencies: 283e0dda311SFrank Wunderlich interrupt-controller: [ interrupts ] 284e0dda311SFrank Wunderlich 285e0dda311SFrank Wunderlich - if: 286e0dda311SFrank Wunderlich properties: 287e0dda311SFrank Wunderlich compatible: 288214537cdSArınç ÜNAL const: mediatek,mt7530 289e0dda311SFrank Wunderlich then: 29079a16c3bSArınç ÜNAL $ref: "#/$defs/mt7530-dsa-port" 291e0dda311SFrank Wunderlich required: 292e0dda311SFrank Wunderlich - core-supply 293e0dda311SFrank Wunderlich - io-supply 294e0dda311SFrank Wunderlich 295f565c54eSArınç ÜNAL - if: 296f565c54eSArınç ÜNAL properties: 297f565c54eSArınç ÜNAL compatible: 298f565c54eSArınç ÜNAL const: mediatek,mt7531 299f565c54eSArınç ÜNAL then: 30079a16c3bSArınç ÜNAL $ref: "#/$defs/mt7531-dsa-port" 301f565c54eSArınç ÜNAL properties: 3020fbca84eSArınç ÜNAL gpio-controller: false 303f565c54eSArınç ÜNAL mediatek,mcm: false 304f565c54eSArınç ÜNAL 305f565c54eSArınç ÜNAL - if: 306f565c54eSArınç ÜNAL properties: 307f565c54eSArınç ÜNAL compatible: 308f565c54eSArınç ÜNAL const: mediatek,mt7621 309f565c54eSArınç ÜNAL then: 31079a16c3bSArınç ÜNAL $ref: "#/$defs/mt7530-dsa-port" 311f565c54eSArınç ÜNAL required: 312f565c54eSArınç ÜNAL - mediatek,mcm 313f565c54eSArınç ÜNAL 314386f5fc9SDaniel Golle - if: 315386f5fc9SDaniel Golle properties: 316386f5fc9SDaniel Golle compatible: 317101a002aSLorenzo Bianconi enum: 318101a002aSLorenzo Bianconi - mediatek,mt7988-switch 319101a002aSLorenzo Bianconi - airoha,en7581-switch 320fef18488SChristian Marangi - airoha,an7583-switch 321386f5fc9SDaniel Golle then: 322588cb646SFrank Wunderlich $ref: "#/$defs/builtin-dsa-port" 323386f5fc9SDaniel Golle properties: 324386f5fc9SDaniel Golle gpio-controller: false 325386f5fc9SDaniel Golle mediatek,mcm: false 326386f5fc9SDaniel Golle reset-names: false 327386f5fc9SDaniel Golle 328e0dda311SFrank WunderlichunevaluatedProperties: false 329e0dda311SFrank Wunderlich 330e0dda311SFrank Wunderlichexamples: 331c9aece04SArınç ÜNAL # Example 1: Standalone MT7530 332e0dda311SFrank Wunderlich - | 333e0dda311SFrank Wunderlich #include <dt-bindings/gpio/gpio.h> 334c9aece04SArınç ÜNAL 335e0dda311SFrank Wunderlich mdio { 336e0dda311SFrank Wunderlich #address-cells = <1>; 337e0dda311SFrank Wunderlich #size-cells = <0>; 338c9aece04SArınç ÜNAL 3393737c6aaSArınç ÜNAL switch@1f { 340e0dda311SFrank Wunderlich compatible = "mediatek,mt7530"; 3413737c6aaSArınç ÜNAL reg = <0x1f>; 342e0dda311SFrank Wunderlich 343c9aece04SArınç ÜNAL reset-gpios = <&pio 33 0>; 344c9aece04SArınç ÜNAL 345e0dda311SFrank Wunderlich core-supply = <&mt6323_vpa_reg>; 346e0dda311SFrank Wunderlich io-supply = <&mt6323_vemc3v3_reg>; 347e0dda311SFrank Wunderlich 348e0dda311SFrank Wunderlich ethernet-ports { 349e0dda311SFrank Wunderlich #address-cells = <1>; 350e0dda311SFrank Wunderlich #size-cells = <0>; 351c9aece04SArınç ÜNAL 352e0dda311SFrank Wunderlich port@0 { 353e0dda311SFrank Wunderlich reg = <0>; 354c9aece04SArınç ÜNAL label = "lan1"; 355e0dda311SFrank Wunderlich }; 356e0dda311SFrank Wunderlich 357e0dda311SFrank Wunderlich port@1 { 358e0dda311SFrank Wunderlich reg = <1>; 359c9aece04SArınç ÜNAL label = "lan2"; 360e0dda311SFrank Wunderlich }; 361e0dda311SFrank Wunderlich 362e0dda311SFrank Wunderlich port@2 { 363e0dda311SFrank Wunderlich reg = <2>; 364c9aece04SArınç ÜNAL label = "lan3"; 365e0dda311SFrank Wunderlich }; 366e0dda311SFrank Wunderlich 367e0dda311SFrank Wunderlich port@3 { 368e0dda311SFrank Wunderlich reg = <3>; 369c9aece04SArınç ÜNAL label = "lan4"; 370c9aece04SArınç ÜNAL }; 371c9aece04SArınç ÜNAL 372c9aece04SArınç ÜNAL port@4 { 373c9aece04SArınç ÜNAL reg = <4>; 374c9aece04SArınç ÜNAL label = "wan"; 375c9aece04SArınç ÜNAL }; 376c9aece04SArınç ÜNAL 377c9aece04SArınç ÜNAL port@6 { 378c9aece04SArınç ÜNAL reg = <6>; 379c9aece04SArınç ÜNAL ethernet = <&gmac0>; 380c9aece04SArınç ÜNAL phy-mode = "rgmii"; 381c9aece04SArınç ÜNAL 382c9aece04SArınç ÜNAL fixed-link { 383c9aece04SArınç ÜNAL speed = <1000>; 384c9aece04SArınç ÜNAL full-duplex; 385c9aece04SArınç ÜNAL pause; 386c9aece04SArınç ÜNAL }; 387c9aece04SArınç ÜNAL }; 388c9aece04SArınç ÜNAL }; 389c9aece04SArınç ÜNAL }; 390c9aece04SArınç ÜNAL }; 391c9aece04SArınç ÜNAL 392c9aece04SArınç ÜNAL # Example 2: MT7530 in MT7623AI SoC 393c9aece04SArınç ÜNAL - | 394c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt2701-resets.h> 395c9aece04SArınç ÜNAL 396c9aece04SArınç ÜNAL mdio { 397c9aece04SArınç ÜNAL #address-cells = <1>; 398c9aece04SArınç ÜNAL #size-cells = <0>; 399c9aece04SArınç ÜNAL 4003737c6aaSArınç ÜNAL switch@1f { 401c9aece04SArınç ÜNAL compatible = "mediatek,mt7530"; 4023737c6aaSArınç ÜNAL reg = <0x1f>; 403c9aece04SArınç ÜNAL 404c9aece04SArınç ÜNAL mediatek,mcm; 405c9aece04SArınç ÜNAL resets = <ðsys MT2701_ETHSYS_MCM_RST>; 406c9aece04SArınç ÜNAL reset-names = "mcm"; 407c9aece04SArınç ÜNAL 408c9aece04SArınç ÜNAL core-supply = <&mt6323_vpa_reg>; 409c9aece04SArınç ÜNAL io-supply = <&mt6323_vemc3v3_reg>; 410c9aece04SArınç ÜNAL 411c9aece04SArınç ÜNAL ethernet-ports { 412c9aece04SArınç ÜNAL #address-cells = <1>; 413c9aece04SArınç ÜNAL #size-cells = <0>; 414c9aece04SArınç ÜNAL 415c9aece04SArınç ÜNAL port@0 { 416c9aece04SArınç ÜNAL reg = <0>; 417c9aece04SArınç ÜNAL label = "lan1"; 418c9aece04SArınç ÜNAL }; 419c9aece04SArınç ÜNAL 420c9aece04SArınç ÜNAL port@1 { 421c9aece04SArınç ÜNAL reg = <1>; 422c9aece04SArınç ÜNAL label = "lan2"; 423c9aece04SArınç ÜNAL }; 424c9aece04SArınç ÜNAL 425c9aece04SArınç ÜNAL port@2 { 426c9aece04SArınç ÜNAL reg = <2>; 427e0dda311SFrank Wunderlich label = "lan3"; 428e0dda311SFrank Wunderlich }; 429e0dda311SFrank Wunderlich 430c9aece04SArınç ÜNAL port@3 { 431c9aece04SArınç ÜNAL reg = <3>; 432c9aece04SArınç ÜNAL label = "lan4"; 433c9aece04SArınç ÜNAL }; 434c9aece04SArınç ÜNAL 435e0dda311SFrank Wunderlich port@4 { 436e0dda311SFrank Wunderlich reg = <4>; 437e0dda311SFrank Wunderlich label = "wan"; 438e0dda311SFrank Wunderlich }; 439e0dda311SFrank Wunderlich 440e0dda311SFrank Wunderlich port@6 { 441e0dda311SFrank Wunderlich reg = <6>; 442e0dda311SFrank Wunderlich ethernet = <&gmac0>; 443e0dda311SFrank Wunderlich phy-mode = "trgmii"; 444e0dda311SFrank Wunderlich 445e0dda311SFrank Wunderlich fixed-link { 446e0dda311SFrank Wunderlich speed = <1000>; 447e0dda311SFrank Wunderlich full-duplex; 448e0dda311SFrank Wunderlich pause; 449e0dda311SFrank Wunderlich }; 450e0dda311SFrank Wunderlich }; 451c9aece04SArınç ÜNAL }; 452c9aece04SArınç ÜNAL }; 453e0dda311SFrank Wunderlich }; 454e0dda311SFrank Wunderlich 455c9aece04SArınç ÜNAL # Example 3: Standalone MT7531 456c9aece04SArınç ÜNAL - | 457c9aece04SArınç ÜNAL #include <dt-bindings/gpio/gpio.h> 458c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/irq.h> 459c9aece04SArınç ÜNAL 460c9aece04SArınç ÜNAL mdio { 461e0dda311SFrank Wunderlich #address-cells = <1>; 462e0dda311SFrank Wunderlich #size-cells = <0>; 463e0dda311SFrank Wunderlich 464c9aece04SArınç ÜNAL switch@0 { 465c9aece04SArınç ÜNAL compatible = "mediatek,mt7531"; 466c9aece04SArınç ÜNAL reg = <0>; 467e0dda311SFrank Wunderlich 468c9aece04SArınç ÜNAL reset-gpios = <&pio 54 0>; 469e0dda311SFrank Wunderlich 470c9aece04SArınç ÜNAL interrupt-controller; 471c9aece04SArınç ÜNAL #interrupt-cells = <1>; 472c9aece04SArınç ÜNAL interrupt-parent = <&pio>; 473c9aece04SArınç ÜNAL interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 474e0dda311SFrank Wunderlich 475e0dda311SFrank Wunderlich ethernet-ports { 476e0dda311SFrank Wunderlich #address-cells = <1>; 477e0dda311SFrank Wunderlich #size-cells = <0>; 478e0dda311SFrank Wunderlich 479e0dda311SFrank Wunderlich port@0 { 480e0dda311SFrank Wunderlich reg = <0>; 481c9aece04SArınç ÜNAL label = "lan1"; 482e0dda311SFrank Wunderlich }; 483e0dda311SFrank Wunderlich 484e0dda311SFrank Wunderlich port@1 { 485e0dda311SFrank Wunderlich reg = <1>; 486c9aece04SArınç ÜNAL label = "lan2"; 487e0dda311SFrank Wunderlich }; 488e0dda311SFrank Wunderlich 489e0dda311SFrank Wunderlich port@2 { 490e0dda311SFrank Wunderlich reg = <2>; 491c9aece04SArınç ÜNAL label = "lan3"; 492e0dda311SFrank Wunderlich }; 493e0dda311SFrank Wunderlich 494e0dda311SFrank Wunderlich port@3 { 495e0dda311SFrank Wunderlich reg = <3>; 496c9aece04SArınç ÜNAL label = "lan4"; 497c9aece04SArınç ÜNAL }; 498c9aece04SArınç ÜNAL 499c9aece04SArınç ÜNAL port@4 { 500c9aece04SArınç ÜNAL reg = <4>; 501c9aece04SArınç ÜNAL label = "wan"; 502c9aece04SArınç ÜNAL }; 503c9aece04SArınç ÜNAL 504c9aece04SArınç ÜNAL port@6 { 505c9aece04SArınç ÜNAL reg = <6>; 506c9aece04SArınç ÜNAL ethernet = <&gmac0>; 507c9aece04SArınç ÜNAL phy-mode = "2500base-x"; 508c9aece04SArınç ÜNAL 509c9aece04SArınç ÜNAL fixed-link { 510c9aece04SArınç ÜNAL speed = <2500>; 511c9aece04SArınç ÜNAL full-duplex; 512c9aece04SArınç ÜNAL pause; 513c9aece04SArınç ÜNAL }; 514c9aece04SArınç ÜNAL }; 515c9aece04SArınç ÜNAL }; 516c9aece04SArınç ÜNAL }; 517c9aece04SArınç ÜNAL }; 518c9aece04SArınç ÜNAL 519c9aece04SArınç ÜNAL # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 520c9aece04SArınç ÜNAL - | 521c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 522c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 523c9aece04SArınç ÜNAL 524c9aece04SArınç ÜNAL mdio { 525c9aece04SArınç ÜNAL #address-cells = <1>; 526c9aece04SArınç ÜNAL #size-cells = <0>; 527c9aece04SArınç ÜNAL 5283737c6aaSArınç ÜNAL switch@1f { 529c9aece04SArınç ÜNAL compatible = "mediatek,mt7621"; 5303737c6aaSArınç ÜNAL reg = <0x1f>; 531c9aece04SArınç ÜNAL 532c9aece04SArınç ÜNAL mediatek,mcm; 533c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 534c9aece04SArınç ÜNAL reset-names = "mcm"; 535c9aece04SArınç ÜNAL 536c9aece04SArınç ÜNAL interrupt-controller; 537c9aece04SArınç ÜNAL #interrupt-cells = <1>; 538c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 539c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 540c9aece04SArınç ÜNAL 541c9aece04SArınç ÜNAL ethernet-ports { 542c9aece04SArınç ÜNAL #address-cells = <1>; 543c9aece04SArınç ÜNAL #size-cells = <0>; 544c9aece04SArınç ÜNAL 545c9aece04SArınç ÜNAL port@0 { 546c9aece04SArınç ÜNAL reg = <0>; 547c9aece04SArınç ÜNAL label = "lan1"; 548c9aece04SArınç ÜNAL }; 549c9aece04SArınç ÜNAL 550c9aece04SArınç ÜNAL port@1 { 551c9aece04SArınç ÜNAL reg = <1>; 552c9aece04SArınç ÜNAL label = "lan2"; 553c9aece04SArınç ÜNAL }; 554c9aece04SArınç ÜNAL 555c9aece04SArınç ÜNAL port@2 { 556c9aece04SArınç ÜNAL reg = <2>; 557e0dda311SFrank Wunderlich label = "lan3"; 558e0dda311SFrank Wunderlich }; 559e0dda311SFrank Wunderlich 560c9aece04SArınç ÜNAL port@3 { 561c9aece04SArınç ÜNAL reg = <3>; 562c9aece04SArınç ÜNAL label = "lan4"; 563c9aece04SArınç ÜNAL }; 564c9aece04SArınç ÜNAL 565e0dda311SFrank Wunderlich port@4 { 566e0dda311SFrank Wunderlich reg = <4>; 567c9aece04SArınç ÜNAL label = "wan"; 568c9aece04SArınç ÜNAL }; 569c9aece04SArınç ÜNAL 570c9aece04SArınç ÜNAL port@6 { 571c9aece04SArınç ÜNAL reg = <6>; 572c9aece04SArınç ÜNAL ethernet = <&gmac0>; 573c9aece04SArınç ÜNAL phy-mode = "trgmii"; 574c9aece04SArınç ÜNAL 575c9aece04SArınç ÜNAL fixed-link { 576c9aece04SArınç ÜNAL speed = <1000>; 577c9aece04SArınç ÜNAL full-duplex; 578c9aece04SArınç ÜNAL pause; 579c9aece04SArınç ÜNAL }; 580c9aece04SArınç ÜNAL }; 581c9aece04SArınç ÜNAL }; 582c9aece04SArınç ÜNAL }; 583c9aece04SArınç ÜNAL }; 584c9aece04SArınç ÜNAL 585c9aece04SArınç ÜNAL # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 586c9aece04SArınç ÜNAL - | 587c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 588c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 589c9aece04SArınç ÜNAL 590c9aece04SArınç ÜNAL ethernet { 591c9aece04SArınç ÜNAL #address-cells = <1>; 592c9aece04SArınç ÜNAL #size-cells = <0>; 593c9aece04SArınç ÜNAL 594c9aece04SArınç ÜNAL pinctrl-names = "default"; 595c9aece04SArınç ÜNAL pinctrl-0 = <&rgmii2_pins>; 596c9aece04SArınç ÜNAL 597c9aece04SArınç ÜNAL mac@1 { 598c9aece04SArınç ÜNAL compatible = "mediatek,eth-mac"; 599c9aece04SArınç ÜNAL reg = <1>; 600c9aece04SArınç ÜNAL 601c9aece04SArınç ÜNAL phy-mode = "rgmii"; 602c9aece04SArınç ÜNAL phy-handle = <&example5_ethphy4>; 603c9aece04SArınç ÜNAL }; 604c9aece04SArınç ÜNAL 605c9aece04SArınç ÜNAL mdio { 606c9aece04SArınç ÜNAL #address-cells = <1>; 607c9aece04SArınç ÜNAL #size-cells = <0>; 608c9aece04SArınç ÜNAL 609c9aece04SArınç ÜNAL /* MT7530's phy4 */ 610c9aece04SArınç ÜNAL example5_ethphy4: ethernet-phy@4 { 611c9aece04SArınç ÜNAL reg = <4>; 612c9aece04SArınç ÜNAL }; 613c9aece04SArınç ÜNAL 6143737c6aaSArınç ÜNAL switch@1f { 615c9aece04SArınç ÜNAL compatible = "mediatek,mt7621"; 6163737c6aaSArınç ÜNAL reg = <0x1f>; 617c9aece04SArınç ÜNAL 618c9aece04SArınç ÜNAL mediatek,mcm; 619c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 620c9aece04SArınç ÜNAL reset-names = "mcm"; 621c9aece04SArınç ÜNAL 622c9aece04SArınç ÜNAL interrupt-controller; 623c9aece04SArınç ÜNAL #interrupt-cells = <1>; 624c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 625c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 626c9aece04SArınç ÜNAL 627c9aece04SArınç ÜNAL ethernet-ports { 628c9aece04SArınç ÜNAL #address-cells = <1>; 629c9aece04SArınç ÜNAL #size-cells = <0>; 630c9aece04SArınç ÜNAL 631c9aece04SArınç ÜNAL port@0 { 632c9aece04SArınç ÜNAL reg = <0>; 633c9aece04SArınç ÜNAL label = "lan1"; 634c9aece04SArınç ÜNAL }; 635c9aece04SArınç ÜNAL 636c9aece04SArınç ÜNAL port@1 { 637c9aece04SArınç ÜNAL reg = <1>; 638c9aece04SArınç ÜNAL label = "lan2"; 639c9aece04SArınç ÜNAL }; 640c9aece04SArınç ÜNAL 641c9aece04SArınç ÜNAL port@2 { 642c9aece04SArınç ÜNAL reg = <2>; 643c9aece04SArınç ÜNAL label = "lan3"; 644c9aece04SArınç ÜNAL }; 645c9aece04SArınç ÜNAL 646c9aece04SArınç ÜNAL port@3 { 647c9aece04SArınç ÜNAL reg = <3>; 648e0dda311SFrank Wunderlich label = "lan4"; 649e0dda311SFrank Wunderlich }; 650c9aece04SArınç ÜNAL 651a71fad0fSArınç ÜNAL /* Commented out, phy4 is connected to gmac1. 652c9aece04SArınç ÜNAL port@4 { 653c9aece04SArınç ÜNAL reg = <4>; 654c9aece04SArınç ÜNAL label = "wan"; 655c9aece04SArınç ÜNAL }; 656e0dda311SFrank Wunderlich */ 657e0dda311SFrank Wunderlich 658e0dda311SFrank Wunderlich port@6 { 659e0dda311SFrank Wunderlich reg = <6>; 660e0dda311SFrank Wunderlich ethernet = <&gmac0>; 661c9aece04SArınç ÜNAL phy-mode = "trgmii"; 662e0dda311SFrank Wunderlich 663e0dda311SFrank Wunderlich fixed-link { 664e0dda311SFrank Wunderlich speed = <1000>; 665e0dda311SFrank Wunderlich full-duplex; 666e0dda311SFrank Wunderlich pause; 667e0dda311SFrank Wunderlich }; 668e0dda311SFrank Wunderlich }; 669e0dda311SFrank Wunderlich }; 670e0dda311SFrank Wunderlich }; 671e0dda311SFrank Wunderlich }; 672e0dda311SFrank Wunderlich }; 673e0dda311SFrank Wunderlich 674c9aece04SArınç ÜNAL # Example 6: MT7621: mux external phy to SoC's gmac1 675e0dda311SFrank Wunderlich - | 676c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 677c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 678e0dda311SFrank Wunderlich 679e0dda311SFrank Wunderlich ethernet { 680e0dda311SFrank Wunderlich #address-cells = <1>; 681e0dda311SFrank Wunderlich #size-cells = <0>; 682c9aece04SArınç ÜNAL 683c9aece04SArınç ÜNAL pinctrl-names = "default"; 684c9aece04SArınç ÜNAL pinctrl-0 = <&rgmii2_pins>; 685c9aece04SArınç ÜNAL 686c9aece04SArınç ÜNAL mac@1 { 687e0dda311SFrank Wunderlich compatible = "mediatek,eth-mac"; 688c9aece04SArınç ÜNAL reg = <1>; 689c9aece04SArınç ÜNAL 690e0dda311SFrank Wunderlich phy-mode = "rgmii"; 691c9aece04SArınç ÜNAL phy-handle = <&example6_ethphy7>; 692e0dda311SFrank Wunderlich }; 693e0dda311SFrank Wunderlich 694c9aece04SArınç ÜNAL mdio { 695e0dda311SFrank Wunderlich #address-cells = <1>; 696e0dda311SFrank Wunderlich #size-cells = <0>; 697e0dda311SFrank Wunderlich 698c9aece04SArınç ÜNAL /* External PHY */ 699c9aece04SArınç ÜNAL example6_ethphy7: ethernet-phy@7 { 700e0dda311SFrank Wunderlich reg = <7>; 701c9aece04SArınç ÜNAL phy-mode = "rgmii"; 702e0dda311SFrank Wunderlich }; 703e0dda311SFrank Wunderlich 7043737c6aaSArınç ÜNAL switch@1f { 705e0dda311SFrank Wunderlich compatible = "mediatek,mt7621"; 7063737c6aaSArınç ÜNAL reg = <0x1f>; 707e0dda311SFrank Wunderlich 708c9aece04SArınç ÜNAL mediatek,mcm; 709c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 710e0dda311SFrank Wunderlich reset-names = "mcm"; 711e0dda311SFrank Wunderlich 712c9aece04SArınç ÜNAL interrupt-controller; 713c9aece04SArınç ÜNAL #interrupt-cells = <1>; 714c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 715c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 716c9aece04SArınç ÜNAL 717e0dda311SFrank Wunderlich ethernet-ports { 718e0dda311SFrank Wunderlich #address-cells = <1>; 719e0dda311SFrank Wunderlich #size-cells = <0>; 720e0dda311SFrank Wunderlich 721e0dda311SFrank Wunderlich port@0 { 722e0dda311SFrank Wunderlich reg = <0>; 723c9aece04SArınç ÜNAL label = "lan1"; 724e0dda311SFrank Wunderlich }; 725e0dda311SFrank Wunderlich 726e0dda311SFrank Wunderlich port@1 { 727e0dda311SFrank Wunderlich reg = <1>; 728c9aece04SArınç ÜNAL label = "lan2"; 729e0dda311SFrank Wunderlich }; 730e0dda311SFrank Wunderlich 731e0dda311SFrank Wunderlich port@2 { 732e0dda311SFrank Wunderlich reg = <2>; 733c9aece04SArınç ÜNAL label = "lan3"; 734e0dda311SFrank Wunderlich }; 735e0dda311SFrank Wunderlich 736e0dda311SFrank Wunderlich port@3 { 737e0dda311SFrank Wunderlich reg = <3>; 738c9aece04SArınç ÜNAL label = "lan4"; 739e0dda311SFrank Wunderlich }; 740e0dda311SFrank Wunderlich 741e0dda311SFrank Wunderlich port@4 { 742e0dda311SFrank Wunderlich reg = <4>; 743c9aece04SArınç ÜNAL label = "wan"; 744c9aece04SArınç ÜNAL }; 745c9aece04SArınç ÜNAL 746c9aece04SArınç ÜNAL port@6 { 747c9aece04SArınç ÜNAL reg = <6>; 748c9aece04SArınç ÜNAL ethernet = <&gmac0>; 749c9aece04SArınç ÜNAL phy-mode = "trgmii"; 750c9aece04SArınç ÜNAL 751c9aece04SArınç ÜNAL fixed-link { 752c9aece04SArınç ÜNAL speed = <1000>; 753c9aece04SArınç ÜNAL full-duplex; 754c9aece04SArınç ÜNAL pause; 755c9aece04SArınç ÜNAL }; 756c9aece04SArınç ÜNAL }; 757c9aece04SArınç ÜNAL }; 758c9aece04SArınç ÜNAL }; 759c9aece04SArınç ÜNAL }; 760c9aece04SArınç ÜNAL }; 761c9aece04SArınç ÜNAL 762c9aece04SArınç ÜNAL # Example 7: MT7621: mux external phy to MT7530's port 5 763c9aece04SArınç ÜNAL - | 764c9aece04SArınç ÜNAL #include <dt-bindings/interrupt-controller/mips-gic.h> 765c9aece04SArınç ÜNAL #include <dt-bindings/reset/mt7621-reset.h> 766c9aece04SArınç ÜNAL 767c9aece04SArınç ÜNAL ethernet { 768c9aece04SArınç ÜNAL #address-cells = <1>; 769c9aece04SArınç ÜNAL #size-cells = <0>; 770c9aece04SArınç ÜNAL 771c9aece04SArınç ÜNAL pinctrl-names = "default"; 772c9aece04SArınç ÜNAL pinctrl-0 = <&rgmii2_pins>; 773c9aece04SArınç ÜNAL 774c9aece04SArınç ÜNAL mdio { 775c9aece04SArınç ÜNAL #address-cells = <1>; 776c9aece04SArınç ÜNAL #size-cells = <0>; 777c9aece04SArınç ÜNAL 778c9aece04SArınç ÜNAL /* External PHY */ 779c9aece04SArınç ÜNAL example7_ethphy7: ethernet-phy@7 { 780c9aece04SArınç ÜNAL reg = <7>; 781c9aece04SArınç ÜNAL phy-mode = "rgmii"; 782c9aece04SArınç ÜNAL }; 783c9aece04SArınç ÜNAL 7843737c6aaSArınç ÜNAL switch@1f { 785c9aece04SArınç ÜNAL compatible = "mediatek,mt7621"; 7863737c6aaSArınç ÜNAL reg = <0x1f>; 787c9aece04SArınç ÜNAL 788c9aece04SArınç ÜNAL mediatek,mcm; 789c9aece04SArınç ÜNAL resets = <&sysc MT7621_RST_MCM>; 790c9aece04SArınç ÜNAL reset-names = "mcm"; 791c9aece04SArınç ÜNAL 792c9aece04SArınç ÜNAL interrupt-controller; 793c9aece04SArınç ÜNAL #interrupt-cells = <1>; 794c9aece04SArınç ÜNAL interrupt-parent = <&gic>; 795c9aece04SArınç ÜNAL interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 796c9aece04SArınç ÜNAL 797c9aece04SArınç ÜNAL ethernet-ports { 798c9aece04SArınç ÜNAL #address-cells = <1>; 799c9aece04SArınç ÜNAL #size-cells = <0>; 800c9aece04SArınç ÜNAL 801c9aece04SArınç ÜNAL port@0 { 802c9aece04SArınç ÜNAL reg = <0>; 803c9aece04SArınç ÜNAL label = "lan1"; 804c9aece04SArınç ÜNAL }; 805c9aece04SArınç ÜNAL 806c9aece04SArınç ÜNAL port@1 { 807c9aece04SArınç ÜNAL reg = <1>; 808c9aece04SArınç ÜNAL label = "lan2"; 809c9aece04SArınç ÜNAL }; 810c9aece04SArınç ÜNAL 811c9aece04SArınç ÜNAL port@2 { 812c9aece04SArınç ÜNAL reg = <2>; 813c9aece04SArınç ÜNAL label = "lan3"; 814c9aece04SArınç ÜNAL }; 815c9aece04SArınç ÜNAL 816c9aece04SArınç ÜNAL port@3 { 817c9aece04SArınç ÜNAL reg = <3>; 818e0dda311SFrank Wunderlich label = "lan4"; 819e0dda311SFrank Wunderlich }; 820e0dda311SFrank Wunderlich 821c9aece04SArınç ÜNAL port@4 { 822c9aece04SArınç ÜNAL reg = <4>; 823c9aece04SArınç ÜNAL label = "wan"; 824c9aece04SArınç ÜNAL }; 825c9aece04SArınç ÜNAL 826e0dda311SFrank Wunderlich port@5 { 827e0dda311SFrank Wunderlich reg = <5>; 828c9aece04SArınç ÜNAL label = "extphy"; 829c9aece04SArınç ÜNAL phy-mode = "rgmii-txid"; 830c9aece04SArınç ÜNAL phy-handle = <&example7_ethphy7>; 831e0dda311SFrank Wunderlich }; 832e0dda311SFrank Wunderlich 833c9aece04SArınç ÜNAL port@6 { 834e0dda311SFrank Wunderlich reg = <6>; 835c9aece04SArınç ÜNAL ethernet = <&gmac0>; 836c9aece04SArınç ÜNAL phy-mode = "trgmii"; 837e0dda311SFrank Wunderlich 838e0dda311SFrank Wunderlich fixed-link { 839e0dda311SFrank Wunderlich speed = <1000>; 840e0dda311SFrank Wunderlich full-duplex; 841e0dda311SFrank Wunderlich pause; 842e0dda311SFrank Wunderlich }; 843e0dda311SFrank Wunderlich }; 844e0dda311SFrank Wunderlich }; 845e0dda311SFrank Wunderlich }; 846e0dda311SFrank Wunderlich }; 847e0dda311SFrank Wunderlich }; 848