1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Marvell MV88E6xxx DSA switch family 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 12description: 13 The Marvell MV88E6xxx switch series has been produced and sold 14 by Marvell since at least 2008. The switch has a few compatibles which 15 just indicate the base address of the switch, then operating systems 16 can investigate switch ID registers to find out which actual version 17 of the switch it is dealing with. 18 19properties: 20 compatible: 21 oneOf: 22 - enum: 23 - marvell,mv88e6085 24 - marvell,mv88e6190 25 - marvell,mv88e6250 26 description: | 27 marvell,mv88e6085: This switch uses base address 0x10. 28 This switch and its siblings will be autodetected from 29 ID registers found in the switch, so only "marvell,mv88e6085" should be 30 specified. This includes the following list of MV88Exxxx switches: 31 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, 6176, 32 6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352 33 marvell,mv88e6190: This switch uses base address 0x00. 34 This switch and its siblings will be autodetected from 35 ID registers found in the switch, so only "marvell,mv88e6190" should be 36 specified. This includes the following list of MV88Exxxx switches: 37 6190, 6190X, 6191, 6290, 6361, 6390, 6390X 38 marvell,mv88e6250: This switch uses base address 0x08 or 0x18. 39 This switch and its siblings will be autodetected from 40 ID registers found in the switch, so only "marvell,mv88e6250" should be 41 specified. This includes the following list of MV88Exxxx switches: 42 6220, 6250 43 - items: 44 - const: marvell,turris-mox-mv88e6085 45 - const: marvell,mv88e6085 46 - items: 47 - const: marvell,turris-mox-mv88e6190 48 - const: marvell,mv88e6190 49 50 reg: 51 maxItems: 1 52 53 eeprom-length: 54 $ref: /schemas/types.yaml#/definitions/uint32 55 description: Set to the length of an EEPROM connected to the switch. Must be 56 set if the switch can not detect the presence and/or size of a connected 57 EEPROM, otherwise optional. 58 59 reset-gpios: 60 description: 61 GPIO to be used to reset the whole device 62 maxItems: 1 63 64 interrupts: 65 description: The switch provides an external interrupt line, but it is 66 not always used by target systems. 67 maxItems: 1 68 69 interrupt-controller: 70 description: The switch has an internal interrupt controller used by 71 the different sub-blocks. 72 73 '#interrupt-cells': 74 description: The internal interrupt controller only supports triggering 75 on active high level interrupts so the second cell must alway be set to 76 IRQ_TYPE_LEVEL_HIGH. 77 const: 2 78 79 mdio: 80 $ref: /schemas/net/mdio.yaml# 81 unevaluatedProperties: false 82 description: Marvell MV88E6xxx switches have an varying combination of 83 internal and external MDIO buses, in some cases a combined bus that 84 can be used both internally and externally. This node is for the 85 primary bus, used internally and sometimes also externally. 86 87 mdio-external: 88 $ref: /schemas/net/mdio.yaml# 89 unevaluatedProperties: false 90 description: Marvell MV88E6xxx switches that have a separate external 91 MDIO bus use this port to access external components on the MDIO bus. 92 93 properties: 94 compatible: 95 const: marvell,mv88e6xxx-mdio-external 96 97 required: 98 - compatible 99 100allOf: 101 - $ref: dsa.yaml#/$defs/ethernet-ports 102 103required: 104 - compatible 105 - reg 106 107unevaluatedProperties: false 108 109examples: 110 - | 111 #include <dt-bindings/gpio/gpio.h> 112 mdio { 113 #address-cells = <1>; 114 #size-cells = <0>; 115 116 ethernet-switch@0 { 117 compatible = "marvell,mv88e6085"; 118 reg = <0>; 119 reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; 120 121 mdio { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 sw_phy0: ethernet-phy@0 { 126 reg = <0x0>; 127 }; 128 129 sw_phy1: ethernet-phy@1 { 130 reg = <0x1>; 131 }; 132 133 sw_phy2: ethernet-phy@2 { 134 reg = <0x2>; 135 }; 136 137 sw_phy3: ethernet-phy@3 { 138 reg = <0x3>; 139 }; 140 }; 141 142 ethernet-ports { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 ethernet-port@0 { 147 reg = <0>; 148 label = "lan4"; 149 phy-handle = <&sw_phy0>; 150 phy-mode = "internal"; 151 }; 152 153 ethernet-port@1 { 154 reg = <1>; 155 label = "lan3"; 156 phy-handle = <&sw_phy1>; 157 phy-mode = "internal"; 158 }; 159 160 ethernet-port@2 { 161 reg = <2>; 162 label = "lan2"; 163 phy-handle = <&sw_phy2>; 164 phy-mode = "internal"; 165 }; 166 167 ethernet-port@3 { 168 reg = <3>; 169 label = "lan1"; 170 phy-handle = <&sw_phy3>; 171 phy-mode = "internal"; 172 }; 173 174 ethernet-port@5 { 175 reg = <5>; 176 ethernet = <&fec>; 177 phy-mode = "rgmii-id"; 178 179 fixed-link { 180 speed = <1000>; 181 full-duplex; 182 }; 183 }; 184 }; 185 }; 186 }; 187 - | 188 #include <dt-bindings/interrupt-controller/irq.h> 189 mdio { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 ethernet-switch@0 { 194 compatible = "marvell,mv88e6190"; 195 #interrupt-cells = <2>; 196 interrupt-controller; 197 interrupt-parent = <&gpio1>; 198 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 199 pinctrl-0 = <&switch_interrupt_pins>; 200 pinctrl-names = "default"; 201 reg = <0>; 202 203 mdio { 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 switch0phy1: ethernet-phy@1 { 208 reg = <0x1>; 209 }; 210 211 switch0phy2: ethernet-phy@2 { 212 reg = <0x2>; 213 }; 214 215 switch0phy3: ethernet-phy@3 { 216 reg = <0x3>; 217 }; 218 219 switch0phy4: ethernet-phy@4 { 220 reg = <0x4>; 221 }; 222 223 switch0phy5: ethernet-phy@5 { 224 reg = <0x5>; 225 }; 226 227 switch0phy6: ethernet-phy@6 { 228 reg = <0x6>; 229 }; 230 231 switch0phy7: ethernet-phy@7 { 232 reg = <0x7>; 233 }; 234 235 switch0phy8: ethernet-phy@8 { 236 reg = <0x8>; 237 }; 238 }; 239 240 mdio-external { 241 compatible = "marvell,mv88e6xxx-mdio-external"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 phy1: ethernet-phy@b { 246 reg = <0xb>; 247 compatible = "ethernet-phy-ieee802.3-c45"; 248 }; 249 250 phy2: ethernet-phy@c { 251 reg = <0xc>; 252 compatible = "ethernet-phy-ieee802.3-c45"; 253 }; 254 }; 255 256 ethernet-ports { 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 ethernet-port@0 { 261 ethernet = <ð0>; 262 phy-mode = "rgmii"; 263 reg = <0>; 264 265 fixed-link { 266 full-duplex; 267 pause; 268 speed = <1000>; 269 }; 270 }; 271 272 ethernet-port@1 { 273 label = "lan1"; 274 phy-handle = <&switch0phy1>; 275 reg = <1>; 276 }; 277 278 ethernet-port@2 { 279 label = "lan2"; 280 phy-handle = <&switch0phy2>; 281 reg = <2>; 282 }; 283 284 ethernet-port@3 { 285 label = "lan3"; 286 phy-handle = <&switch0phy3>; 287 reg = <3>; 288 }; 289 290 ethernet-port@4 { 291 label = "lan4"; 292 phy-handle = <&switch0phy4>; 293 reg = <4>; 294 }; 295 296 ethernet-port@5 { 297 label = "lan5"; 298 phy-handle = <&switch0phy5>; 299 reg = <5>; 300 }; 301 302 ethernet-port@6 { 303 label = "lan6"; 304 phy-handle = <&switch0phy6>; 305 reg = <6>; 306 }; 307 308 ethernet-port@7 { 309 label = "lan7"; 310 phy-handle = <&switch0phy7>; 311 reg = <7>; 312 }; 313 314 ethernet-port@8 { 315 label = "lan8"; 316 phy-handle = <&switch0phy8>; 317 reg = <8>; 318 }; 319 320 ethernet-port@9 { 321 /* 88X3310P external phy */ 322 label = "lan9"; 323 phy-handle = <&phy1>; 324 phy-mode = "xaui"; 325 reg = <9>; 326 }; 327 328 ethernet-port@a { 329 /* 88X3310P external phy */ 330 label = "lan10"; 331 phy-handle = <&phy2>; 332 phy-mode = "xaui"; 333 reg = <0xa>; 334 }; 335 }; 336 }; 337 }; 338