1TI SoC Ethernet Switch Controller Device Tree Bindings 2------------------------------------------------------ 3 4Required properties: 5- compatible : Should be "ti,cpsw" 6- reg : physical base address and size of the cpsw 7 registers map 8- interrupts : property with a value describing the interrupt 9 number 10- interrupt-parent : The parent interrupt controller 11- cpdma_channels : Specifies number of channels in CPDMA 12- host_port_no : Specifies host port shift 13- cpdma_reg_ofs : Specifies CPDMA submodule register offset 14- cpdma_sram_ofs : Specifies CPDMA SRAM offset 15- ale_reg_ofs : Specifies ALE submodule register offset 16- ale_entries : Specifies No of entries ALE can hold 17- host_port_reg_ofs : Specifies host port register offset 18- hw_stats_reg_ofs : Specifies hardware statistics register offset 19- cpts_reg_ofs : Specifies the offset of the CPTS registers 20- bd_ram_ofs : Specifies internal desciptor RAM offset 21- bd_ram_size : Specifies internal descriptor RAM size 22- rx_descs : Specifies number of Rx descriptors 23- mac_control : Specifies Default MAC control register content 24 for the specific platform 25- slaves : Specifies number for slaves 26- cpts_active_slave : Specifies the slave to use for time stamping 27- slave_reg_ofs : Specifies slave register offset 28- sliver_reg_ofs : Specifies slave sliver register offset 29- phy_id : Specifies slave phy id 30- mac-address : Specifies slave MAC address 31 32Optional properties: 33- ti,hwmods : Must be "cpgmac0" 34- no_bd_ram : Must be 0 or 1 35 36Note: "ti,hwmods" field is used to fetch the base address and irq 37resources from TI, omap hwmod data base during device registration. 38Future plan is to migrate hwmod data base contents into device tree 39blob so that, all the required data will be used from device tree dts 40file. 41 42Examples: 43 44 mac: ethernet@4A100000 { 45 compatible = "ti,cpsw"; 46 reg = <0x4A100000 0x1000>; 47 interrupts = <55 0x4>; 48 interrupt-parent = <&intc>; 49 cpdma_channels = <8>; 50 host_port_no = <0>; 51 cpdma_reg_ofs = <0x800>; 52 cpdma_sram_ofs = <0xa00>; 53 ale_reg_ofs = <0xd00>; 54 ale_entries = <1024>; 55 host_port_reg_ofs = <0x108>; 56 hw_stats_reg_ofs = <0x900>; 57 cpts_reg_ofs = <0xc00>; 58 bd_ram_ofs = <0x2000>; 59 bd_ram_size = <0x2000>; 60 no_bd_ram = <0>; 61 rx_descs = <64>; 62 mac_control = <0x20>; 63 slaves = <2>; 64 cpts_active_slave = <0>; 65 cpsw_emac0: slave@0 { 66 slave_reg_ofs = <0x200>; 67 sliver_reg_ofs = <0xd80>; 68 phy_id = "davinci_mdio.16:00"; 69 /* Filled in by U-Boot */ 70 mac-address = [ 00 00 00 00 00 00 ]; 71 }; 72 cpsw_emac1: slave@1 { 73 slave_reg_ofs = <0x300>; 74 sliver_reg_ofs = <0xdc0>; 75 phy_id = "davinci_mdio.16:01"; 76 /* Filled in by U-Boot */ 77 mac-address = [ 00 00 00 00 00 00 ]; 78 }; 79 }; 80 81(or) 82 mac: ethernet@4A100000 { 83 compatible = "ti,cpsw"; 84 ti,hwmods = "cpgmac0"; 85 cpdma_channels = <8>; 86 host_port_no = <0>; 87 cpdma_reg_ofs = <0x800>; 88 cpdma_sram_ofs = <0xa00>; 89 ale_reg_ofs = <0xd00>; 90 ale_entries = <1024>; 91 host_port_reg_ofs = <0x108>; 92 hw_stats_reg_ofs = <0x900>; 93 cpts_reg_ofs = <0xc00>; 94 bd_ram_ofs = <0x2000>; 95 bd_ram_size = <0x2000>; 96 no_bd_ram = <0>; 97 rx_descs = <64>; 98 mac_control = <0x20>; 99 slaves = <2>; 100 cpts_active_slave = <0>; 101 cpsw_emac0: slave@0 { 102 slave_reg_ofs = <0x200>; 103 sliver_reg_ofs = <0xd80>; 104 phy_id = "davinci_mdio.16:00"; 105 /* Filled in by U-Boot */ 106 mac-address = [ 00 00 00 00 00 00 ]; 107 }; 108 cpsw_emac1: slave@1 { 109 slave_reg_ofs = <0x300>; 110 sliver_reg_ofs = <0xdc0>; 111 phy_id = "davinci_mdio.16:01"; 112 /* Filled in by U-Boot */ 113 mac-address = [ 00 00 00 00 00 00 ]; 114 }; 115 }; 116