12eb32b0aSMugunthan V NTI SoC Ethernet Switch Controller Device Tree Bindings 22eb32b0aSMugunthan V N------------------------------------------------------ 32eb32b0aSMugunthan V N 42eb32b0aSMugunthan V NRequired properties: 52eb32b0aSMugunthan V N- compatible : Should be "ti,cpsw" 62eb32b0aSMugunthan V N- reg : physical base address and size of the cpsw 72eb32b0aSMugunthan V N registers map 82eb32b0aSMugunthan V N- interrupts : property with a value describing the interrupt 92eb32b0aSMugunthan V N number 102eb32b0aSMugunthan V N- interrupt-parent : The parent interrupt controller 112eb32b0aSMugunthan V N- cpdma_channels : Specifies number of channels in CPDMA 122eb32b0aSMugunthan V N- host_port_no : Specifies host port shift 132eb32b0aSMugunthan V N- cpdma_reg_ofs : Specifies CPDMA submodule register offset 14*e07b94f1SMugunthan V N- cpdma_sram_ofs : Specifies CPDMA SRAM offset 152eb32b0aSMugunthan V N- ale_reg_ofs : Specifies ALE submodule register offset 162eb32b0aSMugunthan V N- ale_entries : Specifies No of entries ALE can hold 172eb32b0aSMugunthan V N- host_port_reg_ofs : Specifies host port register offset 182eb32b0aSMugunthan V N- hw_stats_reg_ofs : Specifies hardware statistics register offset 192eb32b0aSMugunthan V N- bd_ram_ofs : Specifies internal desciptor RAM offset 202eb32b0aSMugunthan V N- bd_ram_size : Specifies internal descriptor RAM size 212eb32b0aSMugunthan V N- rx_descs : Specifies number of Rx descriptors 222eb32b0aSMugunthan V N- mac_control : Specifies Default MAC control register content 232eb32b0aSMugunthan V N for the specific platform 242eb32b0aSMugunthan V N- slaves : Specifies number for slaves 252eb32b0aSMugunthan V N- slave_reg_ofs : Specifies slave register offset 262eb32b0aSMugunthan V N- sliver_reg_ofs : Specifies slave sliver register offset 272eb32b0aSMugunthan V N- phy_id : Specifies slave phy id 282eb32b0aSMugunthan V N- mac-address : Specifies slave MAC address 292eb32b0aSMugunthan V N 302eb32b0aSMugunthan V NOptional properties: 312eb32b0aSMugunthan V N- ti,hwmods : Must be "cpgmac0" 322eb32b0aSMugunthan V N- no_bd_ram : Must be 0 or 1 332eb32b0aSMugunthan V N 342eb32b0aSMugunthan V NNote: "ti,hwmods" field is used to fetch the base address and irq 352eb32b0aSMugunthan V Nresources from TI, omap hwmod data base during device registration. 362eb32b0aSMugunthan V NFuture plan is to migrate hwmod data base contents into device tree 372eb32b0aSMugunthan V Nblob so that, all the required data will be used from device tree dts 382eb32b0aSMugunthan V Nfile. 392eb32b0aSMugunthan V N 402eb32b0aSMugunthan V NExamples: 412eb32b0aSMugunthan V N 422eb32b0aSMugunthan V N mac: ethernet@4A100000 { 432eb32b0aSMugunthan V N compatible = "ti,cpsw"; 442eb32b0aSMugunthan V N reg = <0x4A100000 0x1000>; 452eb32b0aSMugunthan V N interrupts = <55 0x4>; 462eb32b0aSMugunthan V N interrupt-parent = <&intc>; 47*e07b94f1SMugunthan V N cpdma_channels = <8>; 48*e07b94f1SMugunthan V N host_port_no = <0>; 49*e07b94f1SMugunthan V N cpdma_reg_ofs = <0x800>; 50*e07b94f1SMugunthan V N cpdma_sram_ofs = <0xa00>; 51*e07b94f1SMugunthan V N ale_reg_ofs = <0xd00>; 52*e07b94f1SMugunthan V N ale_entries = <1024>; 53*e07b94f1SMugunthan V N host_port_reg_ofs = <0x108>; 54*e07b94f1SMugunthan V N hw_stats_reg_ofs = <0x900>; 55*e07b94f1SMugunthan V N bd_ram_ofs = <0x2000>; 56*e07b94f1SMugunthan V N bd_ram_size = <0x2000>; 57*e07b94f1SMugunthan V N no_bd_ram = <0>; 58*e07b94f1SMugunthan V N rx_descs = <64>; 59*e07b94f1SMugunthan V N mac_control = <0x20>; 60*e07b94f1SMugunthan V N slaves = <2>; 61*e07b94f1SMugunthan V N cpsw_emac0: slave@0 { 62*e07b94f1SMugunthan V N slave_reg_ofs = <0x208>; 63*e07b94f1SMugunthan V N sliver_reg_ofs = <0xd80>; 64*e07b94f1SMugunthan V N phy_id = "davinci_mdio.16:00"; 65*e07b94f1SMugunthan V N /* Filled in by U-Boot */ 66*e07b94f1SMugunthan V N mac-address = [ 00 00 00 00 00 00 ]; 672eb32b0aSMugunthan V N }; 68*e07b94f1SMugunthan V N cpsw_emac1: slave@1 { 69*e07b94f1SMugunthan V N slave_reg_ofs = <0x308>; 70*e07b94f1SMugunthan V N sliver_reg_ofs = <0xdc0>; 71*e07b94f1SMugunthan V N phy_id = "davinci_mdio.16:01"; 72*e07b94f1SMugunthan V N /* Filled in by U-Boot */ 73*e07b94f1SMugunthan V N mac-address = [ 00 00 00 00 00 00 ]; 742eb32b0aSMugunthan V N }; 752eb32b0aSMugunthan V N }; 762eb32b0aSMugunthan V N 772eb32b0aSMugunthan V N(or) 782eb32b0aSMugunthan V N mac: ethernet@4A100000 { 792eb32b0aSMugunthan V N compatible = "ti,cpsw"; 802eb32b0aSMugunthan V N ti,hwmods = "cpgmac0"; 81*e07b94f1SMugunthan V N cpdma_channels = <8>; 82*e07b94f1SMugunthan V N host_port_no = <0>; 83*e07b94f1SMugunthan V N cpdma_reg_ofs = <0x800>; 84*e07b94f1SMugunthan V N cpdma_sram_ofs = <0xa00>; 85*e07b94f1SMugunthan V N ale_reg_ofs = <0xd00>; 86*e07b94f1SMugunthan V N ale_entries = <1024>; 87*e07b94f1SMugunthan V N host_port_reg_ofs = <0x108>; 88*e07b94f1SMugunthan V N hw_stats_reg_ofs = <0x900>; 89*e07b94f1SMugunthan V N bd_ram_ofs = <0x2000>; 90*e07b94f1SMugunthan V N bd_ram_size = <0x2000>; 91*e07b94f1SMugunthan V N no_bd_ram = <0>; 92*e07b94f1SMugunthan V N rx_descs = <64>; 93*e07b94f1SMugunthan V N mac_control = <0x20>; 94*e07b94f1SMugunthan V N slaves = <2>; 95*e07b94f1SMugunthan V N cpsw_emac0: slave@0 { 96*e07b94f1SMugunthan V N slave_reg_ofs = <0x208>; 97*e07b94f1SMugunthan V N sliver_reg_ofs = <0xd80>; 98*e07b94f1SMugunthan V N phy_id = "davinci_mdio.16:00"; 99*e07b94f1SMugunthan V N /* Filled in by U-Boot */ 100*e07b94f1SMugunthan V N mac-address = [ 00 00 00 00 00 00 ]; 1012eb32b0aSMugunthan V N }; 102*e07b94f1SMugunthan V N cpsw_emac1: slave@1 { 103*e07b94f1SMugunthan V N slave_reg_ofs = <0x308>; 104*e07b94f1SMugunthan V N sliver_reg_ofs = <0xdc0>; 105*e07b94f1SMugunthan V N phy_id = "davinci_mdio.16:01"; 106*e07b94f1SMugunthan V N /* Filled in by U-Boot */ 107*e07b94f1SMugunthan V N mac-address = [ 00 00 00 00 00 00 ]; 1082eb32b0aSMugunthan V N }; 1092eb32b0aSMugunthan V N }; 110