1*2eb32b0aSMugunthan V NTI SoC Ethernet Switch Controller Device Tree Bindings 2*2eb32b0aSMugunthan V N------------------------------------------------------ 3*2eb32b0aSMugunthan V N 4*2eb32b0aSMugunthan V NRequired properties: 5*2eb32b0aSMugunthan V N- compatible : Should be "ti,cpsw" 6*2eb32b0aSMugunthan V N- reg : physical base address and size of the cpsw 7*2eb32b0aSMugunthan V N registers map 8*2eb32b0aSMugunthan V N- interrupts : property with a value describing the interrupt 9*2eb32b0aSMugunthan V N number 10*2eb32b0aSMugunthan V N- interrupt-parent : The parent interrupt controller 11*2eb32b0aSMugunthan V N- cpdma_channels : Specifies number of channels in CPDMA 12*2eb32b0aSMugunthan V N- host_port_no : Specifies host port shift 13*2eb32b0aSMugunthan V N- cpdma_reg_ofs : Specifies CPDMA submodule register offset 14*2eb32b0aSMugunthan V N- ale_reg_ofs : Specifies ALE submodule register offset 15*2eb32b0aSMugunthan V N- ale_entries : Specifies No of entries ALE can hold 16*2eb32b0aSMugunthan V N- host_port_reg_ofs : Specifies host port register offset 17*2eb32b0aSMugunthan V N- hw_stats_reg_ofs : Specifies hardware statistics register offset 18*2eb32b0aSMugunthan V N- bd_ram_ofs : Specifies internal desciptor RAM offset 19*2eb32b0aSMugunthan V N- bd_ram_size : Specifies internal descriptor RAM size 20*2eb32b0aSMugunthan V N- rx_descs : Specifies number of Rx descriptors 21*2eb32b0aSMugunthan V N- mac_control : Specifies Default MAC control register content 22*2eb32b0aSMugunthan V N for the specific platform 23*2eb32b0aSMugunthan V N- slaves : Specifies number for slaves 24*2eb32b0aSMugunthan V N- slave_reg_ofs : Specifies slave register offset 25*2eb32b0aSMugunthan V N- sliver_reg_ofs : Specifies slave sliver register offset 26*2eb32b0aSMugunthan V N- phy_id : Specifies slave phy id 27*2eb32b0aSMugunthan V N- mac-address : Specifies slave MAC address 28*2eb32b0aSMugunthan V N 29*2eb32b0aSMugunthan V NOptional properties: 30*2eb32b0aSMugunthan V N- ti,hwmods : Must be "cpgmac0" 31*2eb32b0aSMugunthan V N- no_bd_ram : Must be 0 or 1 32*2eb32b0aSMugunthan V N 33*2eb32b0aSMugunthan V NNote: "ti,hwmods" field is used to fetch the base address and irq 34*2eb32b0aSMugunthan V Nresources from TI, omap hwmod data base during device registration. 35*2eb32b0aSMugunthan V NFuture plan is to migrate hwmod data base contents into device tree 36*2eb32b0aSMugunthan V Nblob so that, all the required data will be used from device tree dts 37*2eb32b0aSMugunthan V Nfile. 38*2eb32b0aSMugunthan V N 39*2eb32b0aSMugunthan V NExamples: 40*2eb32b0aSMugunthan V N 41*2eb32b0aSMugunthan V N mac: ethernet@4A100000 { 42*2eb32b0aSMugunthan V N compatible = "ti,cpsw"; 43*2eb32b0aSMugunthan V N reg = <0x4A100000 0x1000>; 44*2eb32b0aSMugunthan V N interrupts = <55 0x4>; 45*2eb32b0aSMugunthan V N interrupt-parent = <&intc>; 46*2eb32b0aSMugunthan V N cpdma_channels = 8; 47*2eb32b0aSMugunthan V N host_port_no = 0; 48*2eb32b0aSMugunthan V N cpdma_reg_ofs = 0x800; 49*2eb32b0aSMugunthan V N ale_reg_ofs = 0xd00; 50*2eb32b0aSMugunthan V N ale_entries = 1024; 51*2eb32b0aSMugunthan V N host_port_reg_ofs = 0x108; 52*2eb32b0aSMugunthan V N hw_stats_reg_ofs = 0x900; 53*2eb32b0aSMugunthan V N bd_ram_ofs = 0x2000; 54*2eb32b0aSMugunthan V N bd_ram_size = 0x2000; 55*2eb32b0aSMugunthan V N no_bd_ram = 0; 56*2eb32b0aSMugunthan V N rx_descs = 64; 57*2eb32b0aSMugunthan V N mac_control = 0x20; 58*2eb32b0aSMugunthan V N slaves = 2; 59*2eb32b0aSMugunthan V N slave@0 { 60*2eb32b0aSMugunthan V N slave_reg_ofs = 0x208; 61*2eb32b0aSMugunthan V N sliver_reg_ofs = 0xd80; 62*2eb32b0aSMugunthan V N phy_id = "davinci_mdio-0:00" 63*2eb32b0aSMugunthan V N mac-address = [00 04 9F 01 1B B8]; 64*2eb32b0aSMugunthan V N }; 65*2eb32b0aSMugunthan V N slave@1 { 66*2eb32b0aSMugunthan V N slave_reg_ofs = 0x208; 67*2eb32b0aSMugunthan V N sliver_reg_ofs = 0xd80; 68*2eb32b0aSMugunthan V N phy_id = "davinci_mdio-0:01" 69*2eb32b0aSMugunthan V N mac-address = [00 04 9F 01 1B B9]; 70*2eb32b0aSMugunthan V N }; 71*2eb32b0aSMugunthan V N }; 72*2eb32b0aSMugunthan V N 73*2eb32b0aSMugunthan V N(or) 74*2eb32b0aSMugunthan V N 75*2eb32b0aSMugunthan V N mac: ethernet@4A100000 { 76*2eb32b0aSMugunthan V N compatible = "ti,cpsw"; 77*2eb32b0aSMugunthan V N ti,hwmods = "cpgmac0"; 78*2eb32b0aSMugunthan V N cpdma_channels = 8; 79*2eb32b0aSMugunthan V N host_port_no = 0; 80*2eb32b0aSMugunthan V N cpdma_reg_ofs = 0x800; 81*2eb32b0aSMugunthan V N ale_reg_ofs = 0xd00; 82*2eb32b0aSMugunthan V N ale_entries = 1024; 83*2eb32b0aSMugunthan V N host_port_reg_ofs = 0x108; 84*2eb32b0aSMugunthan V N hw_stats_reg_ofs = 0x900; 85*2eb32b0aSMugunthan V N bd_ram_ofs = 0x2000; 86*2eb32b0aSMugunthan V N bd_ram_size = 0x2000; 87*2eb32b0aSMugunthan V N no_bd_ram = 0; 88*2eb32b0aSMugunthan V N rx_descs = 64; 89*2eb32b0aSMugunthan V N mac_control = 0x20; 90*2eb32b0aSMugunthan V N slaves = 2; 91*2eb32b0aSMugunthan V N slave@0 { 92*2eb32b0aSMugunthan V N slave_reg_ofs = 0x208; 93*2eb32b0aSMugunthan V N sliver_reg_ofs = 0xd80; 94*2eb32b0aSMugunthan V N phy_id = "davinci_mdio-0:00" 95*2eb32b0aSMugunthan V N mac-address = [00 04 9F 01 1B B8]; 96*2eb32b0aSMugunthan V N }; 97*2eb32b0aSMugunthan V N slave@1 { 98*2eb32b0aSMugunthan V N slave_reg_ofs = 0x208; 99*2eb32b0aSMugunthan V N sliver_reg_ofs = 0xd80; 100*2eb32b0aSMugunthan V N phy_id = "davinci_mdio-0:01" 101*2eb32b0aSMugunthan V N mac-address = [00 04 9F 01 1B B9]; 102*2eb32b0aSMugunthan V N }; 103*2eb32b0aSMugunthan V N 104*2eb32b0aSMugunthan V N }; 105