1*5892cd13SMugunthan V NTI CPSW Phy mode Selection Device Tree Bindings 2*5892cd13SMugunthan V N----------------------------------------------- 3*5892cd13SMugunthan V N 4*5892cd13SMugunthan V NRequired properties: 5*5892cd13SMugunthan V N- compatible : Should be "ti,am3352-cpsw-phy-sel" 6*5892cd13SMugunthan V N- reg : physical base address and size of the cpsw 7*5892cd13SMugunthan V N registers map 8*5892cd13SMugunthan V N- reg-names : names of the register map given in "reg" node 9*5892cd13SMugunthan V N 10*5892cd13SMugunthan V NOptional properties: 11*5892cd13SMugunthan V N-rmii-clock-ext : If present, the driver will configure the RMII 12*5892cd13SMugunthan V N interface to external clock usage 13*5892cd13SMugunthan V N 14*5892cd13SMugunthan V NExamples: 15*5892cd13SMugunthan V N 16*5892cd13SMugunthan V N phy_sel: cpsw-phy-sel@44e10650 { 17*5892cd13SMugunthan V N compatible = "ti,am3352-cpsw-phy-sel"; 18*5892cd13SMugunthan V N reg= <0x44e10650 0x4>; 19*5892cd13SMugunthan V N reg-names = "gmii-sel"; 20*5892cd13SMugunthan V N }; 21*5892cd13SMugunthan V N 22*5892cd13SMugunthan V N(or) 23*5892cd13SMugunthan V N phy_sel: cpsw-phy-sel@44e10650 { 24*5892cd13SMugunthan V N compatible = "ti,am3352-cpsw-phy-sel"; 25*5892cd13SMugunthan V N reg= <0x44e10650 0x4>; 26*5892cd13SMugunthan V N reg-names = "gmii-sel"; 27*5892cd13SMugunthan V N rmii-clock-ext; 28*5892cd13SMugunthan V N }; 29