1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/cdns,macb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence MACB/GEM Ethernet controller 8 9maintainers: 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 12 13properties: 14 compatible: 15 oneOf: 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 20 21 - items: 22 - enum: 23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 25 - const: cdns,gem # Generic 26 deprecated: true 27 28 - items: 29 - enum: 30 - xlnx,versal-gem # Xilinx Versal 31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC 32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 33 - const: cdns,gem # Generic 34 35 - items: 36 - enum: 37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs 38 - cdns,sam9x60-macb # Microchip sam9x60 SoC 39 - microchip,mpfs-macb # Microchip PolarFire SoC 40 - const: cdns,macb # Generic 41 42 - items: 43 - enum: 44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs 45 - enum: 46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs. 47 - const: cdns,macb # Generic 48 49 - enum: 50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs 51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs 52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs 53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs 54 - cdns,at32ap7000-macb # Other 10/100 usage or use the generic form 55 - cdns,np4-macb # NP4 SoC devices 56 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface 57 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 58 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC 59 - cdns,emac # Generic 60 - cdns,gem # Generic 61 - cdns,macb # Generic 62 63 reg: 64 minItems: 1 65 items: 66 - description: Basic register set 67 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC 68 69 interrupts: 70 minItems: 1 71 maxItems: 8 72 description: One interrupt per available hardware queue 73 74 clocks: 75 minItems: 1 76 maxItems: 5 77 78 clock-names: 79 minItems: 1 80 items: 81 - enum: [ ether_clk, hclk, pclk ] 82 - enum: [ hclk, pclk ] 83 - const: tx_clk 84 - enum: [ rx_clk, tsu_clk ] 85 - const: tsu_clk 86 87 local-mac-address: true 88 89 phy-mode: true 90 91 phy-handle: true 92 93 phys: 94 maxItems: 1 95 96 resets: 97 maxItems: 1 98 description: 99 Recommended with ZynqMP, specify reset control for this 100 controller instance with zynqmp-reset driver. 101 102 reset-names: 103 maxItems: 1 104 105 fixed-link: true 106 107 iommus: 108 maxItems: 1 109 110 power-domains: 111 maxItems: 1 112 113 '#address-cells': 114 const: 1 115 116 '#size-cells': 117 const: 0 118 119 mdio: 120 type: object 121 description: 122 Node containing PHY children. If this node is not present, then PHYs will 123 be direct children. 124 125patternProperties: 126 "^ethernet-phy@[0-9a-f]$": 127 type: object 128 $ref: ethernet-phy.yaml# 129 130 properties: 131 reset-gpios: true 132 133 magic-packet: 134 type: boolean 135 description: 136 Indicates that the hardware supports waking up via magic packet. 137 138 unevaluatedProperties: false 139 140required: 141 - compatible 142 - reg 143 - interrupts 144 - clocks 145 - clock-names 146 - phy-mode 147 148allOf: 149 - $ref: ethernet-controller.yaml# 150 151 - if: 152 not: 153 properties: 154 compatible: 155 contains: 156 const: sifive,fu540-c000-gem 157 then: 158 properties: 159 reg: 160 maxItems: 1 161 162unevaluatedProperties: false 163 164examples: 165 - | 166 macb0: ethernet@fffc4000 { 167 compatible = "cdns,at32ap7000-macb"; 168 reg = <0xfffc4000 0x4000>; 169 interrupts = <21>; 170 phy-mode = "rmii"; 171 local-mac-address = [3a 0e 03 04 05 06]; 172 clock-names = "pclk", "hclk", "tx_clk"; 173 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 ethernet-phy@1 { 178 reg = <0x1>; 179 reset-gpios = <&pioE 6 1>; 180 }; 181 }; 182 183 - | 184 #include <dt-bindings/clock/xlnx-zynqmp-clk.h> 185 #include <dt-bindings/power/xlnx-zynqmp-power.h> 186 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 187 #include <dt-bindings/phy/phy.h> 188 189 bus { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 gem1: ethernet@ff0c0000 { 193 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 194 interrupt-parent = <&gic>; 195 interrupts = <0 59 4>, <0 59 4>; 196 reg = <0x0 0xff0c0000 0x0 0x1000>; 197 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, 198 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, 199 <&zynqmp_clk GEM_TSU>; 200 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 iommus = <&smmu 0x875>; 204 power-domains = <&zynqmp_firmware PD_ETH_1>; 205 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 206 reset-names = "gem1_rst"; 207 status = "okay"; 208 phy-mode = "sgmii"; 209 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>; 210 fixed-link { 211 speed = <1000>; 212 full-duplex; 213 pause; 214 }; 215 }; 216 }; 217