1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/cdns,macb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence MACB/GEM Ethernet controller 8 9maintainers: 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 12 13properties: 14 compatible: 15 oneOf: 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 20 21 - items: 22 - enum: 23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 25 - const: cdns,gem # Generic 26 deprecated: true 27 28 - items: 29 - enum: 30 - xlnx,versal-gem # Xilinx Versal 31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC 32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 33 - const: cdns,gem # Generic 34 35 - items: 36 - enum: 37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs 38 - cdns,sam9x60-macb # Microchip sam9x60 SoC 39 - microchip,mpfs-macb # Microchip PolarFire SoC 40 - const: cdns,macb # Generic 41 42 - items: 43 - enum: 44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs 45 - enum: 46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs. 47 - const: cdns,macb # Generic 48 49 - enum: 50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs 51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs 52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs 53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs 54 - cdns,np4-macb # NP4 SoC devices 55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface 56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 57 - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface 58 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC 59 - cdns,emac # Generic 60 - cdns,gem # Generic 61 - cdns,macb # Generic 62 63 - items: 64 - enum: 65 - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface 66 - microchip,sama7d65-gem # Microchip SAMA7D65 gigabit ethernet interface 67 - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 68 69 reg: 70 minItems: 1 71 items: 72 - description: Basic register set 73 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC 74 75 interrupts: 76 minItems: 1 77 maxItems: 8 78 description: One interrupt per available hardware queue 79 80 clocks: 81 minItems: 1 82 maxItems: 5 83 84 clock-names: 85 minItems: 1 86 items: 87 - enum: [ ether_clk, hclk, pclk ] 88 - enum: [ hclk, pclk ] 89 - const: tx_clk 90 - enum: [ rx_clk, tsu_clk ] 91 - const: tsu_clk 92 93 local-mac-address: true 94 95 phy-mode: true 96 97 phy-handle: true 98 99 phys: 100 maxItems: 1 101 102 resets: 103 maxItems: 1 104 description: 105 Recommended with ZynqMP, specify reset control for this 106 controller instance with zynqmp-reset driver. 107 108 reset-names: 109 maxItems: 1 110 111 fixed-link: true 112 113 iommus: 114 maxItems: 1 115 116 power-domains: 117 maxItems: 1 118 119 cdns,refclk-ext: 120 type: boolean 121 description: 122 This selects if the REFCLK for RMII is provided by an external source. 123 For RGMII mode this selects if the 125MHz REF clock is provided by an external 124 source. 125 126 cdns,rx-watermark: 127 $ref: /schemas/types.yaml#/definitions/uint32 128 description: 129 When the receive partial store and forward mode is activated, 130 the receiver will only begin to forward the packet to the external 131 AHB or AXI slave when enough packet data is stored in the SRAM packet buffer. 132 rx-watermark corresponds to the number of SRAM buffer locations, 133 that need to be filled, before the forwarding process is activated. 134 Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes. 135 136 '#address-cells': 137 const: 1 138 139 '#size-cells': 140 const: 0 141 142 mdio: 143 type: object 144 description: 145 Node containing PHY children. If this node is not present, then PHYs will 146 be direct children. 147 148patternProperties: 149 "^ethernet-phy@[0-9a-f]$": 150 type: object 151 $ref: ethernet-phy.yaml# 152 153 properties: 154 reset-gpios: true 155 156 magic-packet: 157 type: boolean 158 deprecated: true 159 description: 160 Indicates that the hardware supports waking up via magic packet. 161 162 unevaluatedProperties: false 163 164required: 165 - compatible 166 - reg 167 - interrupts 168 - clocks 169 - clock-names 170 - phy-mode 171 172allOf: 173 - $ref: ethernet-controller.yaml# 174 175 - if: 176 not: 177 properties: 178 compatible: 179 contains: 180 const: sifive,fu540-c000-gem 181 then: 182 properties: 183 reg: 184 maxItems: 1 185 186unevaluatedProperties: false 187 188examples: 189 - | 190 macb0: ethernet@fffc4000 { 191 compatible = "cdns,macb"; 192 reg = <0xfffc4000 0x4000>; 193 interrupts = <21>; 194 cdns,rx-watermark = <0x44>; 195 phy-mode = "rmii"; 196 local-mac-address = [3a 0e 03 04 05 06]; 197 clock-names = "pclk", "hclk", "tx_clk"; 198 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 ethernet-phy@1 { 203 reg = <0x1>; 204 reset-gpios = <&pioE 6 1>; 205 }; 206 }; 207 208 - | 209 #include <dt-bindings/power/xlnx-zynqmp-power.h> 210 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 211 #include <dt-bindings/phy/phy.h> 212 213 bus { 214 #address-cells = <2>; 215 #size-cells = <2>; 216 gem1: ethernet@ff0c0000 { 217 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 218 interrupt-parent = <&gic>; 219 interrupts = <0 59 4>, <0 59 4>; 220 reg = <0x0 0xff0c0000 0x0 0x1000>; 221 clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, 222 <&zynqmp_clk 51>, <&zynqmp_clk 50>, 223 <&zynqmp_clk 44>; 224 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 iommus = <&smmu 0x875>; 228 power-domains = <&zynqmp_firmware PD_ETH_1>; 229 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 230 reset-names = "gem1_rst"; 231 phy-mode = "sgmii"; 232 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>; 233 fixed-link { 234 speed = <1000>; 235 full-duplex; 236 pause; 237 }; 238 }; 239 }; 240