xref: /linux/Documentation/devicetree/bindings/net/cdns,macb.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/cdns,macb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence MACB/GEM Ethernet controller
8
9maintainers:
10  - Nicolas Ferre <nicolas.ferre@microchip.com>
11  - Claudiu Beznea <claudiu.beznea@microchip.com>
12
13properties:
14  compatible:
15    oneOf:
16      - items:
17          - enum:
18              - cdns,at91rm9200-emac  # Atmel at91rm9200 SoC
19          - const: cdns,emac          # Generic
20
21      - items:
22          - enum:
23              - cdns,zynq-gem         # Xilinx Zynq-7xxx SoC
24              - cdns,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
25          - const: cdns,gem           # Generic
26        deprecated: true
27
28      - items:
29          - enum:
30              - xlnx,versal-gem       # Xilinx Versal
31              - xlnx,zynq-gem         # Xilinx Zynq-7xxx SoC
32              - xlnx,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
33          - const: cdns,gem           # Generic
34
35      - items:
36          - enum:
37              - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38              - cdns,sam9x60-macb     # Microchip sam9x60 SoC
39              - microchip,mpfs-macb   # Microchip PolarFire SoC
40          - const: cdns,macb          # Generic
41      - items:
42          - const: microchip,pic64gx-macb # Microchip PIC64GX SoC
43          - const: microchip,mpfs-macb    # Microchip PolarFire SoC
44          - const: cdns,macb              # Generic
45      - items:
46          - enum:
47              - atmel,sama5d3-macb    # 10/100Mbit IP on Atmel sama5d3 SoCs
48          - enum:
49              - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
50          - const: cdns,macb          # Generic
51
52      - enum:
53          - atmel,sama5d2-gem         # GEM IP (10/100) on Atmel sama5d2 SoCs
54          - atmel,sama5d29-gem        # GEM XL IP (10/100) on Atmel sama5d29 SoCs
55          - atmel,sama5d3-gem         # Gigabit IP on Atmel sama5d3 SoCs
56          - atmel,sama5d4-gem         # GEM IP (10/100) on Atmel sama5d4 SoCs
57          - cdns,emac                 # Generic
58          - cdns,gem                  # Generic
59          - cdns,macb                 # Generic
60          - cdns,np4-macb             # NP4 SoC devices
61          - microchip,sama7g5-emac    # Microchip SAMA7G5 ethernet interface
62          - microchip,sama7g5-gem     # Microchip SAMA7G5 gigabit ethernet interface
63          - mobileye,eyeq5-gem        # Mobileye EyeQ5 SoCs
64          - raspberrypi,rp1-gem       # Raspberry Pi RP1 gigabit ethernet interface
65          - sifive,fu540-c000-gem     # SiFive FU540-C000 SoC
66
67      - items:
68          - enum:
69              - microchip,sam9x7-gem     # Microchip SAM9X7 gigabit ethernet interface
70              - microchip,sama7d65-gem   # Microchip SAMA7D65 gigabit ethernet interface
71          - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
72
73      - items:
74          - const: microchip,pic64hpsc-gem # Microchip PIC64-HPSC
75          - const: cdns,gem
76      - items:
77          - const: microchip,pic64hx-gem   # Microchip PIC64HX
78          - const: microchip,pic64hpsc-gem # Microchip PIC64-HPSC
79          - const: cdns,gem
80
81  reg:
82    minItems: 1
83    items:
84      - description: Basic register set
85      - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
86
87  interrupts:
88    minItems: 1
89    maxItems: 8
90    description: One interrupt per available hardware queue
91
92  clocks:
93    minItems: 1
94    maxItems: 5
95
96  clock-names:
97    minItems: 1
98    items:
99      - enum: [ ether_clk, hclk, pclk ]
100      - enum: [ hclk, pclk ]
101      - enum: [ tx_clk, tsu_clk ]
102      - enum: [ rx_clk, tsu_clk ]
103      - const: tsu_clk
104
105  local-mac-address: true
106
107  phy-mode: true
108
109  phy-handle: true
110
111  phys:
112    maxItems: 1
113
114  resets:
115    maxItems: 1
116    description:
117      Recommended with ZynqMP, specify reset control for this
118      controller instance with zynqmp-reset driver.
119
120  reset-names:
121    maxItems: 1
122
123  fixed-link: true
124
125  iommus:
126    maxItems: 1
127
128  power-domains:
129    maxItems: 1
130
131  cdns,refclk-ext:
132    type: boolean
133    deprecated: true
134    description: |
135     This selects if the REFCLK for RMII is provided by an external source.
136     For RGMII mode this selects if the 125MHz REF clock is provided by an external
137     source.
138
139     This property has been replaced by cdns,refclk-source, as it only works
140     for devices that use an internal reference clock by default.
141
142  cdns,refclk-source:
143    $ref: /schemas/types.yaml#/definitions/string
144    enum:
145      - internal
146      - external
147    description:
148      Select whether or not the refclk for RGMII or RMII is provided by an
149      internal or external source. The default is device specific.
150
151  cdns,rx-watermark:
152    $ref: /schemas/types.yaml#/definitions/uint32
153    description:
154      When the receive partial store and forward mode is activated,
155      the receiver will only begin to forward the packet to the external
156      AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
157      rx-watermark corresponds to the number of SRAM buffer locations,
158      that need to be filled, before the forwarding process is activated.
159      Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
160
161  cdns,timer-adjust:
162    type: boolean
163    description:
164      Set when the hardware is operating in timer-adjust mode, where the timer
165      is controlled by the gem_tsu_inc_ctrl and gem_tsu_ms inputs.
166
167  '#address-cells':
168    const: 1
169
170  '#size-cells':
171    const: 0
172
173  mdio:
174    type: object
175    description:
176      Node containing PHY children. If this node is not present, then PHYs will
177      be direct children.
178
179patternProperties:
180  "^ethernet-phy@[0-9a-f]$":
181    type: object
182    $ref: ethernet-phy.yaml#
183
184    properties:
185      reset-gpios: true
186
187      magic-packet:
188        type: boolean
189        deprecated: true
190        description:
191          Indicates that the hardware supports waking up via magic packet.
192
193    unevaluatedProperties: false
194
195required:
196  - compatible
197  - reg
198  - interrupts
199  - clocks
200  - clock-names
201  - phy-mode
202
203allOf:
204  - $ref: ethernet-controller.yaml#
205
206  - if:
207      not:
208        properties:
209          compatible:
210            contains:
211              const: sifive,fu540-c000-gem
212    then:
213      properties:
214        reg:
215          maxItems: 1
216  - if:
217      not:
218        properties:
219          compatible:
220            contains:
221              const: microchip,mpfs-macb
222    then:
223      properties:
224        cdns,timer-adjust: false
225
226  - if:
227      properties:
228        compatible:
229          contains:
230            const: mobileye,eyeq5-gem
231    then:
232      required:
233        - phys
234
235  - if:
236      properties:
237        compatible:
238          contains:
239            const: microchip,pic64hpsc-gem
240    then:
241      patternProperties:
242        "^ethernet-phy@[0-9a-f]$": false
243      properties:
244        mdio: false
245
246  - if:
247      not:
248        properties:
249          compatible:
250            contains:
251              enum:
252                - microchip,sama7g5-gem
253                - microchip,sama7g5-emac
254    then:
255      properties:
256        cdns,refclk-source: false
257
258  - if:
259      not:
260        properties:
261          compatible:
262            contains:
263              const: microchip,sama7g5-gem
264    then:
265      properties:
266        cdns,refclk-ext: false
267
268  - if:
269      properties:
270        compatible:
271          contains:
272            enum:
273              - microchip,sama7g5-emac
274    then:
275      properties:
276        cdns,refclk-source:
277          default: external
278    else:
279      properties:
280        cdns,refclk-source:
281          default: internal
282
283unevaluatedProperties: false
284
285examples:
286  - |
287    macb0: ethernet@fffc4000 {
288            compatible = "cdns,macb";
289            reg = <0xfffc4000 0x4000>;
290            interrupts = <21>;
291            cdns,rx-watermark = <0x44>;
292            phy-mode = "rmii";
293            local-mac-address = [3a 0e 03 04 05 06];
294            clock-names = "pclk", "hclk", "tx_clk";
295            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
296            #address-cells = <1>;
297            #size-cells = <0>;
298
299            ethernet-phy@1 {
300                    reg = <0x1>;
301                    reset-gpios = <&pioE 6 1>;
302            };
303    };
304
305  - |
306    #include <dt-bindings/power/xlnx-zynqmp-power.h>
307    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
308    #include <dt-bindings/phy/phy.h>
309
310    bus {
311            #address-cells = <2>;
312            #size-cells = <2>;
313            gem1: ethernet@ff0c0000 {
314                    compatible = "xlnx,zynqmp-gem", "cdns,gem";
315                    interrupt-parent = <&gic>;
316                    interrupts = <0 59 4>, <0 59 4>;
317                    reg = <0x0 0xff0c0000 0x0 0x1000>;
318                    clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>,
319                             <&zynqmp_clk 51>, <&zynqmp_clk 50>,
320                             <&zynqmp_clk 44>;
321                    clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
322                    #address-cells = <1>;
323                    #size-cells = <0>;
324                    iommus = <&smmu 0x875>;
325                    power-domains = <&zynqmp_firmware PD_ETH_1>;
326                    resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
327                    reset-names = "gem1_rst";
328                    phy-mode = "sgmii";
329                    phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
330                    fixed-link {
331                            speed = <1000>;
332                            full-duplex;
333                            pause;
334                    };
335            };
336    };
337