1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/cdns,macb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence MACB/GEM Ethernet controller 8 9maintainers: 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 12 13properties: 14 compatible: 15 oneOf: 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 20 21 - items: 22 - enum: 23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 25 - const: cdns,gem # Generic 26 deprecated: true 27 28 - items: 29 - enum: 30 - xlnx,versal-gem # Xilinx Versal 31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC 32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 33 - const: cdns,gem # Generic 34 35 - items: 36 - enum: 37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs 38 - cdns,sam9x60-macb # Microchip sam9x60 SoC 39 - microchip,mpfs-macb # Microchip PolarFire SoC 40 - const: cdns,macb # Generic 41 - items: 42 - const: microchip,pic64gx-macb # Microchip PIC64GX SoC 43 - const: microchip,mpfs-macb # Microchip PolarFire SoC 44 - const: cdns,macb # Generic 45 - items: 46 - enum: 47 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs 48 - enum: 49 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs. 50 - const: cdns,macb # Generic 51 52 - enum: 53 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs 54 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs 55 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs 56 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs 57 - cdns,emac # Generic 58 - cdns,gem # Generic 59 - cdns,macb # Generic 60 - cdns,np4-macb # NP4 SoC devices 61 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface 62 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 63 - mobileye,eyeq5-gem # Mobileye EyeQ5 SoCs 64 - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface 65 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC 66 67 - items: 68 - enum: 69 - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface 70 - microchip,sama7d65-gem # Microchip SAMA7D65 gigabit ethernet interface 71 - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 72 73 - items: 74 - const: microchip,pic64hpsc-gem # Microchip PIC64-HPSC 75 - const: cdns,gem 76 - items: 77 - const: microchip,pic64hx-gem # Microchip PIC64HX 78 - const: microchip,pic64hpsc-gem # Microchip PIC64-HPSC 79 - const: cdns,gem 80 81 reg: 82 minItems: 1 83 items: 84 - description: Basic register set 85 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC 86 87 interrupts: 88 minItems: 1 89 maxItems: 8 90 description: One interrupt per available hardware queue 91 92 clocks: 93 minItems: 1 94 maxItems: 5 95 96 clock-names: 97 minItems: 1 98 items: 99 - enum: [ ether_clk, hclk, pclk ] 100 - enum: [ hclk, pclk ] 101 - enum: [ tx_clk, tsu_clk ] 102 - enum: [ rx_clk, tsu_clk ] 103 - const: tsu_clk 104 105 local-mac-address: true 106 107 phy-mode: true 108 109 phy-handle: true 110 111 phys: 112 maxItems: 1 113 114 resets: 115 maxItems: 1 116 description: 117 Recommended with ZynqMP, specify reset control for this 118 controller instance with zynqmp-reset driver. 119 120 reset-names: 121 maxItems: 1 122 123 fixed-link: true 124 125 iommus: 126 maxItems: 1 127 128 power-domains: 129 maxItems: 1 130 131 cdns,refclk-ext: 132 type: boolean 133 description: 134 This selects if the REFCLK for RMII is provided by an external source. 135 For RGMII mode this selects if the 125MHz REF clock is provided by an external 136 source. 137 138 cdns,rx-watermark: 139 $ref: /schemas/types.yaml#/definitions/uint32 140 description: 141 When the receive partial store and forward mode is activated, 142 the receiver will only begin to forward the packet to the external 143 AHB or AXI slave when enough packet data is stored in the SRAM packet buffer. 144 rx-watermark corresponds to the number of SRAM buffer locations, 145 that need to be filled, before the forwarding process is activated. 146 Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes. 147 148 '#address-cells': 149 const: 1 150 151 '#size-cells': 152 const: 0 153 154 mdio: 155 type: object 156 description: 157 Node containing PHY children. If this node is not present, then PHYs will 158 be direct children. 159 160patternProperties: 161 "^ethernet-phy@[0-9a-f]$": 162 type: object 163 $ref: ethernet-phy.yaml# 164 165 properties: 166 reset-gpios: true 167 168 magic-packet: 169 type: boolean 170 deprecated: true 171 description: 172 Indicates that the hardware supports waking up via magic packet. 173 174 unevaluatedProperties: false 175 176required: 177 - compatible 178 - reg 179 - interrupts 180 - clocks 181 - clock-names 182 - phy-mode 183 184allOf: 185 - $ref: ethernet-controller.yaml# 186 187 - if: 188 not: 189 properties: 190 compatible: 191 contains: 192 const: sifive,fu540-c000-gem 193 then: 194 properties: 195 reg: 196 maxItems: 1 197 198 - if: 199 properties: 200 compatible: 201 contains: 202 const: mobileye,eyeq5-gem 203 then: 204 required: 205 - phys 206 207 - if: 208 properties: 209 compatible: 210 contains: 211 const: microchip,pic64hpsc-gem 212 then: 213 patternProperties: 214 "^ethernet-phy@[0-9a-f]$": false 215 properties: 216 mdio: false 217 218unevaluatedProperties: false 219 220examples: 221 - | 222 macb0: ethernet@fffc4000 { 223 compatible = "cdns,macb"; 224 reg = <0xfffc4000 0x4000>; 225 interrupts = <21>; 226 cdns,rx-watermark = <0x44>; 227 phy-mode = "rmii"; 228 local-mac-address = [3a 0e 03 04 05 06]; 229 clock-names = "pclk", "hclk", "tx_clk"; 230 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 ethernet-phy@1 { 235 reg = <0x1>; 236 reset-gpios = <&pioE 6 1>; 237 }; 238 }; 239 240 - | 241 #include <dt-bindings/power/xlnx-zynqmp-power.h> 242 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 243 #include <dt-bindings/phy/phy.h> 244 245 bus { 246 #address-cells = <2>; 247 #size-cells = <2>; 248 gem1: ethernet@ff0c0000 { 249 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 250 interrupt-parent = <&gic>; 251 interrupts = <0 59 4>, <0 59 4>; 252 reg = <0x0 0xff0c0000 0x0 0x1000>; 253 clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, 254 <&zynqmp_clk 51>, <&zynqmp_clk 50>, 255 <&zynqmp_clk 44>; 256 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 iommus = <&smmu 0x875>; 260 power-domains = <&zynqmp_firmware PD_ETH_1>; 261 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 262 reset-names = "gem1_rst"; 263 phy-mode = "sgmii"; 264 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>; 265 fixed-link { 266 speed = <1000>; 267 full-duplex; 268 pause; 269 }; 270 }; 271 }; 272