1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/cdns,macb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence MACB/GEM Ethernet controller 8 9maintainers: 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 12 13properties: 14 compatible: 15 oneOf: 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 20 21 - items: 22 - enum: 23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 25 - const: cdns,gem # Generic 26 deprecated: true 27 28 - items: 29 - enum: 30 - xlnx,versal-gem # Xilinx Versal 31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC 32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 33 - const: cdns,gem # Generic 34 35 - items: 36 - enum: 37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs 38 - cdns,sam9x60-macb # Microchip sam9x60 SoC 39 - microchip,mpfs-macb # Microchip PolarFire SoC 40 - const: cdns,macb # Generic 41 42 - items: 43 - enum: 44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs 45 - enum: 46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs. 47 - const: cdns,macb # Generic 48 49 - enum: 50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs 51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs 52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs 53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs 54 - cdns,np4-macb # NP4 SoC devices 55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface 56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC 58 - cdns,emac # Generic 59 - cdns,gem # Generic 60 - cdns,macb # Generic 61 62 - items: 63 - enum: 64 - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface 65 - microchip,sama7d65-gem # Microchip SAMA7D65 gigabit ethernet interface 66 - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 67 68 reg: 69 minItems: 1 70 items: 71 - description: Basic register set 72 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC 73 74 interrupts: 75 minItems: 1 76 maxItems: 8 77 description: One interrupt per available hardware queue 78 79 clocks: 80 minItems: 1 81 maxItems: 5 82 83 clock-names: 84 minItems: 1 85 items: 86 - enum: [ ether_clk, hclk, pclk ] 87 - enum: [ hclk, pclk ] 88 - const: tx_clk 89 - enum: [ rx_clk, tsu_clk ] 90 - const: tsu_clk 91 92 local-mac-address: true 93 94 phy-mode: true 95 96 phy-handle: true 97 98 phys: 99 maxItems: 1 100 101 resets: 102 maxItems: 1 103 description: 104 Recommended with ZynqMP, specify reset control for this 105 controller instance with zynqmp-reset driver. 106 107 reset-names: 108 maxItems: 1 109 110 fixed-link: true 111 112 iommus: 113 maxItems: 1 114 115 power-domains: 116 maxItems: 1 117 118 cdns,rx-watermark: 119 $ref: /schemas/types.yaml#/definitions/uint32 120 description: 121 When the receive partial store and forward mode is activated, 122 the receiver will only begin to forward the packet to the external 123 AHB or AXI slave when enough packet data is stored in the SRAM packet buffer. 124 rx-watermark corresponds to the number of SRAM buffer locations, 125 that need to be filled, before the forwarding process is activated. 126 Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes. 127 128 '#address-cells': 129 const: 1 130 131 '#size-cells': 132 const: 0 133 134 mdio: 135 type: object 136 description: 137 Node containing PHY children. If this node is not present, then PHYs will 138 be direct children. 139 140patternProperties: 141 "^ethernet-phy@[0-9a-f]$": 142 type: object 143 $ref: ethernet-phy.yaml# 144 145 properties: 146 reset-gpios: true 147 148 magic-packet: 149 type: boolean 150 deprecated: true 151 description: 152 Indicates that the hardware supports waking up via magic packet. 153 154 unevaluatedProperties: false 155 156required: 157 - compatible 158 - reg 159 - interrupts 160 - clocks 161 - clock-names 162 - phy-mode 163 164allOf: 165 - $ref: ethernet-controller.yaml# 166 167 - if: 168 not: 169 properties: 170 compatible: 171 contains: 172 const: sifive,fu540-c000-gem 173 then: 174 properties: 175 reg: 176 maxItems: 1 177 178unevaluatedProperties: false 179 180examples: 181 - | 182 macb0: ethernet@fffc4000 { 183 compatible = "cdns,macb"; 184 reg = <0xfffc4000 0x4000>; 185 interrupts = <21>; 186 cdns,rx-watermark = <0x44>; 187 phy-mode = "rmii"; 188 local-mac-address = [3a 0e 03 04 05 06]; 189 clock-names = "pclk", "hclk", "tx_clk"; 190 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 194 ethernet-phy@1 { 195 reg = <0x1>; 196 reset-gpios = <&pioE 6 1>; 197 }; 198 }; 199 200 - | 201 #include <dt-bindings/power/xlnx-zynqmp-power.h> 202 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 203 #include <dt-bindings/phy/phy.h> 204 205 bus { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 gem1: ethernet@ff0c0000 { 209 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 210 interrupt-parent = <&gic>; 211 interrupts = <0 59 4>, <0 59 4>; 212 reg = <0x0 0xff0c0000 0x0 0x1000>; 213 clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, 214 <&zynqmp_clk 51>, <&zynqmp_clk 50>, 215 <&zynqmp_clk 44>; 216 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 iommus = <&smmu 0x875>; 220 power-domains = <&zynqmp_firmware PD_ETH_1>; 221 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 222 reset-names = "gem1_rst"; 223 phy-mode = "sgmii"; 224 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>; 225 fixed-link { 226 speed = <1000>; 227 full-duplex; 228 pause; 229 }; 230 }; 231 }; 232