xref: /linux/Documentation/devicetree/bindings/net/cdns,macb.yaml (revision 0e50474fa514822e9d990874e554bf8043a201d7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/cdns,macb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence MACB/GEM Ethernet controller
8
9maintainers:
10  - Nicolas Ferre <nicolas.ferre@microchip.com>
11  - Claudiu Beznea <claudiu.beznea@microchip.com>
12
13properties:
14  compatible:
15    oneOf:
16      - items:
17          - enum:
18              - cdns,at91rm9200-emac  # Atmel at91rm9200 SoC
19          - const: cdns,emac          # Generic
20
21      - items:
22          - enum:
23              - cdns,zynq-gem         # Xilinx Zynq-7xxx SoC
24              - cdns,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
25          - const: cdns,gem           # Generic
26        deprecated: true
27
28      - items:
29          - enum:
30              - xlnx,versal-gem       # Xilinx Versal
31              - xlnx,zynq-gem         # Xilinx Zynq-7xxx SoC
32              - xlnx,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
33          - const: cdns,gem           # Generic
34
35      - items:
36          - enum:
37              - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38              - cdns,sam9x60-macb     # Microchip sam9x60 SoC
39              - microchip,mpfs-macb   # Microchip PolarFire SoC
40          - const: cdns,macb          # Generic
41
42      - items:
43          - enum:
44              - atmel,sama5d3-macb    # 10/100Mbit IP on Atmel sama5d3 SoCs
45          - enum:
46              - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
47          - const: cdns,macb          # Generic
48
49      - enum:
50          - atmel,sama5d2-gem         # GEM IP (10/100) on Atmel sama5d2 SoCs
51          - atmel,sama5d29-gem        # GEM XL IP (10/100) on Atmel sama5d29 SoCs
52          - atmel,sama5d3-gem         # Gigabit IP on Atmel sama5d3 SoCs
53          - atmel,sama5d4-gem         # GEM IP (10/100) on Atmel sama5d4 SoCs
54          - cdns,emac                 # Generic
55          - cdns,gem                  # Generic
56          - cdns,macb                 # Generic
57          - cdns,np4-macb             # NP4 SoC devices
58          - microchip,sama7g5-emac    # Microchip SAMA7G5 ethernet interface
59          - microchip,sama7g5-gem     # Microchip SAMA7G5 gigabit ethernet interface
60          - mobileye,eyeq5-gem        # Mobileye EyeQ5 SoCs
61          - raspberrypi,rp1-gem       # Raspberry Pi RP1 gigabit ethernet interface
62          - sifive,fu540-c000-gem     # SiFive FU540-C000 SoC
63
64      - items:
65          - enum:
66              - microchip,sam9x7-gem     # Microchip SAM9X7 gigabit ethernet interface
67              - microchip,sama7d65-gem   # Microchip SAMA7D65 gigabit ethernet interface
68          - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
69
70  reg:
71    minItems: 1
72    items:
73      - description: Basic register set
74      - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
75
76  interrupts:
77    minItems: 1
78    maxItems: 8
79    description: One interrupt per available hardware queue
80
81  clocks:
82    minItems: 1
83    maxItems: 5
84
85  clock-names:
86    minItems: 1
87    items:
88      - enum: [ ether_clk, hclk, pclk ]
89      - enum: [ hclk, pclk ]
90      - enum: [ tx_clk, tsu_clk ]
91      - enum: [ rx_clk, tsu_clk ]
92      - const: tsu_clk
93
94  local-mac-address: true
95
96  phy-mode: true
97
98  phy-handle: true
99
100  phys:
101    maxItems: 1
102
103  resets:
104    maxItems: 1
105    description:
106      Recommended with ZynqMP, specify reset control for this
107      controller instance with zynqmp-reset driver.
108
109  reset-names:
110    maxItems: 1
111
112  fixed-link: true
113
114  iommus:
115    maxItems: 1
116
117  power-domains:
118    maxItems: 1
119
120  cdns,refclk-ext:
121    type: boolean
122    description:
123      This selects if the REFCLK for RMII is provided by an external source.
124      For RGMII mode this selects if the 125MHz REF clock is provided by an external
125      source.
126
127  cdns,rx-watermark:
128    $ref: /schemas/types.yaml#/definitions/uint32
129    description:
130      When the receive partial store and forward mode is activated,
131      the receiver will only begin to forward the packet to the external
132      AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
133      rx-watermark corresponds to the number of SRAM buffer locations,
134      that need to be filled, before the forwarding process is activated.
135      Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
136
137  '#address-cells':
138    const: 1
139
140  '#size-cells':
141    const: 0
142
143  mdio:
144    type: object
145    description:
146      Node containing PHY children. If this node is not present, then PHYs will
147      be direct children.
148
149patternProperties:
150  "^ethernet-phy@[0-9a-f]$":
151    type: object
152    $ref: ethernet-phy.yaml#
153
154    properties:
155      reset-gpios: true
156
157      magic-packet:
158        type: boolean
159        deprecated: true
160        description:
161          Indicates that the hardware supports waking up via magic packet.
162
163    unevaluatedProperties: false
164
165required:
166  - compatible
167  - reg
168  - interrupts
169  - clocks
170  - clock-names
171  - phy-mode
172
173allOf:
174  - $ref: ethernet-controller.yaml#
175
176  - if:
177      not:
178        properties:
179          compatible:
180            contains:
181              const: sifive,fu540-c000-gem
182    then:
183      properties:
184        reg:
185          maxItems: 1
186
187  - if:
188      properties:
189        compatible:
190          contains:
191            const: mobileye,eyeq5-gem
192    then:
193      required:
194        - phys
195
196unevaluatedProperties: false
197
198examples:
199  - |
200    macb0: ethernet@fffc4000 {
201            compatible = "cdns,macb";
202            reg = <0xfffc4000 0x4000>;
203            interrupts = <21>;
204            cdns,rx-watermark = <0x44>;
205            phy-mode = "rmii";
206            local-mac-address = [3a 0e 03 04 05 06];
207            clock-names = "pclk", "hclk", "tx_clk";
208            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
209            #address-cells = <1>;
210            #size-cells = <0>;
211
212            ethernet-phy@1 {
213                    reg = <0x1>;
214                    reset-gpios = <&pioE 6 1>;
215            };
216    };
217
218  - |
219    #include <dt-bindings/power/xlnx-zynqmp-power.h>
220    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
221    #include <dt-bindings/phy/phy.h>
222
223    bus {
224            #address-cells = <2>;
225            #size-cells = <2>;
226            gem1: ethernet@ff0c0000 {
227                    compatible = "xlnx,zynqmp-gem", "cdns,gem";
228                    interrupt-parent = <&gic>;
229                    interrupts = <0 59 4>, <0 59 4>;
230                    reg = <0x0 0xff0c0000 0x0 0x1000>;
231                    clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>,
232                             <&zynqmp_clk 51>, <&zynqmp_clk 50>,
233                             <&zynqmp_clk 44>;
234                    clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
235                    #address-cells = <1>;
236                    #size-cells = <0>;
237                    iommus = <&smmu 0x875>;
238                    power-domains = <&zynqmp_firmware PD_ETH_1>;
239                    resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
240                    reset-names = "gem1_rst";
241                    phy-mode = "sgmii";
242                    phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
243                    fixed-link {
244                            speed = <1000>;
245                            full-duplex;
246                            pause;
247                    };
248            };
249    };
250