xref: /linux/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml (revision e43250c0ac8123e4560ac39777cd94ab6e75ee23)
1*e43250c0SDario Binacchi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*e43250c0SDario Binacchi%YAML 1.2
3*e43250c0SDario Binacchi---
4*e43250c0SDario Binacchi$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5*e43250c0SDario Binacchi$schema: http://devicetree.org/meta-schemas/core.yaml#
6*e43250c0SDario Binacchi
7*e43250c0SDario Binacchititle: STMicroelectronics bxCAN controller
8*e43250c0SDario Binacchi
9*e43250c0SDario Binacchidescription: STMicroelectronics BxCAN controller for CAN bus
10*e43250c0SDario Binacchi
11*e43250c0SDario Binacchimaintainers:
12*e43250c0SDario Binacchi  - Dario Binacchi <dario.binacchi@amarulasolutions.com>
13*e43250c0SDario Binacchi
14*e43250c0SDario BinacchiallOf:
15*e43250c0SDario Binacchi  - $ref: can-controller.yaml#
16*e43250c0SDario Binacchi
17*e43250c0SDario Binacchiproperties:
18*e43250c0SDario Binacchi  compatible:
19*e43250c0SDario Binacchi    enum:
20*e43250c0SDario Binacchi      - st,stm32f4-bxcan
21*e43250c0SDario Binacchi
22*e43250c0SDario Binacchi  st,can-primary:
23*e43250c0SDario Binacchi    description:
24*e43250c0SDario Binacchi      Primary and secondary mode of the bxCAN peripheral is only relevant
25*e43250c0SDario Binacchi      if the chip has two CAN peripherals. In that case they share some
26*e43250c0SDario Binacchi      of the required logic.
27*e43250c0SDario Binacchi      To avoid misunderstandings, it should be noted that ST documentation
28*e43250c0SDario Binacchi      uses the terms master/slave instead of primary/secondary.
29*e43250c0SDario Binacchi    type: boolean
30*e43250c0SDario Binacchi
31*e43250c0SDario Binacchi  reg:
32*e43250c0SDario Binacchi    maxItems: 1
33*e43250c0SDario Binacchi
34*e43250c0SDario Binacchi  interrupts:
35*e43250c0SDario Binacchi    items:
36*e43250c0SDario Binacchi      - description: transmit interrupt
37*e43250c0SDario Binacchi      - description: FIFO 0 receive interrupt
38*e43250c0SDario Binacchi      - description: FIFO 1 receive interrupt
39*e43250c0SDario Binacchi      - description: status change error interrupt
40*e43250c0SDario Binacchi
41*e43250c0SDario Binacchi  interrupt-names:
42*e43250c0SDario Binacchi    items:
43*e43250c0SDario Binacchi      - const: tx
44*e43250c0SDario Binacchi      - const: rx0
45*e43250c0SDario Binacchi      - const: rx1
46*e43250c0SDario Binacchi      - const: sce
47*e43250c0SDario Binacchi
48*e43250c0SDario Binacchi  resets:
49*e43250c0SDario Binacchi    maxItems: 1
50*e43250c0SDario Binacchi
51*e43250c0SDario Binacchi  clocks:
52*e43250c0SDario Binacchi    maxItems: 1
53*e43250c0SDario Binacchi
54*e43250c0SDario Binacchi  st,gcan:
55*e43250c0SDario Binacchi    $ref: /schemas/types.yaml#/definitions/phandle-array
56*e43250c0SDario Binacchi    description:
57*e43250c0SDario Binacchi      The phandle to the gcan node which allows to access the 512-bytes
58*e43250c0SDario Binacchi      SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
59*e43250c0SDario Binacchi      secondary) in dual CAN peripheral configuration.
60*e43250c0SDario Binacchi
61*e43250c0SDario Binacchirequired:
62*e43250c0SDario Binacchi  - compatible
63*e43250c0SDario Binacchi  - reg
64*e43250c0SDario Binacchi  - interrupts
65*e43250c0SDario Binacchi  - resets
66*e43250c0SDario Binacchi  - clocks
67*e43250c0SDario Binacchi  - st,gcan
68*e43250c0SDario Binacchi
69*e43250c0SDario BinacchiadditionalProperties: false
70*e43250c0SDario Binacchi
71*e43250c0SDario Binacchiexamples:
72*e43250c0SDario Binacchi  - |
73*e43250c0SDario Binacchi    #include <dt-bindings/clock/stm32fx-clock.h>
74*e43250c0SDario Binacchi    #include <dt-bindings/mfd/stm32f4-rcc.h>
75*e43250c0SDario Binacchi
76*e43250c0SDario Binacchi    can1: can@40006400 {
77*e43250c0SDario Binacchi        compatible = "st,stm32f4-bxcan";
78*e43250c0SDario Binacchi        reg = <0x40006400 0x200>;
79*e43250c0SDario Binacchi        interrupts = <19>, <20>, <21>, <22>;
80*e43250c0SDario Binacchi        interrupt-names = "tx", "rx0", "rx1", "sce";
81*e43250c0SDario Binacchi        resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
82*e43250c0SDario Binacchi        clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
83*e43250c0SDario Binacchi        st,can-primary;
84*e43250c0SDario Binacchi        st,gcan = <&gcan>;
85*e43250c0SDario Binacchi    };
86