1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/can/fsl,flexcan.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: 8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC). 9 10maintainers: 11 - Marc Kleine-Budde <mkl@pengutronix.de> 12 13properties: 14 compatible: 15 oneOf: 16 - enum: 17 - fsl,imx95-flexcan 18 - fsl,imx93-flexcan 19 - fsl,imx8qm-flexcan 20 - fsl,imx8mp-flexcan 21 - fsl,imx6q-flexcan 22 - fsl,imx28-flexcan 23 - fsl,imx25-flexcan 24 - fsl,p1010-flexcan 25 - fsl,vf610-flexcan 26 - fsl,ls1021ar2-flexcan 27 - fsl,lx2160ar1-flexcan 28 - nxp,s32g2-flexcan 29 - items: 30 - enum: 31 - fsl,imx53-flexcan 32 - fsl,imx35-flexcan 33 - const: fsl,imx25-flexcan 34 - items: 35 - enum: 36 - fsl,imx7d-flexcan 37 - fsl,imx6ul-flexcan 38 - fsl,imx6sx-flexcan 39 - const: fsl,imx6q-flexcan 40 - items: 41 - enum: 42 - fsl,ls1028ar1-flexcan 43 - const: fsl,lx2160ar1-flexcan 44 - items: 45 - enum: 46 - nxp,s32g3-flexcan 47 - const: nxp,s32g2-flexcan 48 49 reg: 50 maxItems: 1 51 52 interrupts: 53 minItems: 1 54 maxItems: 4 55 56 interrupt-names: 57 minItems: 1 58 maxItems: 4 59 60 clocks: 61 maxItems: 2 62 63 clock-names: 64 items: 65 - const: ipg 66 - const: per 67 68 clock-frequency: 69 description: | 70 The oscillator frequency driving the flexcan device, filled in by the 71 boot loader. This property should only be used the used operating system 72 doesn't support the clocks and clock-names property. 73 74 power-domains: 75 maxItems: 1 76 77 xceiver-supply: 78 description: Regulator that powers the CAN transceiver. 79 80 big-endian: 81 $ref: /schemas/types.yaml#/definitions/flag 82 description: | 83 This means the registers of FlexCAN controller are big endian. This is 84 optional property.i.e. if this property is not present in device tree 85 node then controller is assumed to be little endian. If this property is 86 present then controller is assumed to be big endian. 87 88 can-transceiver: 89 $ref: can-transceiver.yaml# 90 unevaluatedProperties: false 91 92 fsl,stop-mode: 93 description: | 94 Register bits of stop mode control. 95 96 The format should be as follows: 97 <gpr req_gpr req_bit> 98 gpr is the phandle to general purpose register node. 99 req_gpr is the gpr register offset of CAN stop request. 100 req_bit is the bit offset of CAN stop request. 101 $ref: /schemas/types.yaml#/definitions/phandle-array 102 items: 103 - items: 104 - description: The 'gpr' is the phandle to general purpose register node. 105 - description: The 'req_gpr' is the gpr register offset of CAN stop request. 106 maximum: 0xff 107 - description: The 'req_bit' is the bit offset of CAN stop request. 108 maximum: 0x1f 109 110 fsl,clk-source: 111 description: | 112 Select the clock source to the CAN Protocol Engine (PE). It's SoC 113 implementation dependent. Refer to RM for detailed definition. If this 114 property is not set in device tree node then driver selects clock source 1 115 by default. 116 0: clock source 0 (oscillator clock) 117 1: clock source 1 (peripheral clock) 118 $ref: /schemas/types.yaml#/definitions/uint8 119 default: 1 120 minimum: 0 121 maximum: 1 122 123 wakeup-source: 124 $ref: /schemas/types.yaml#/definitions/flag 125 description: 126 Enable CAN remote wakeup. 127 128 fsl,scu-index: 129 description: | 130 The scu index of CAN instance. 131 For SoCs with SCU support, need setup stop mode via SCU firmware, so this 132 property can help indicate a resource. It supports up to 3 CAN instances 133 now. 134 $ref: /schemas/types.yaml#/definitions/uint8 135 minimum: 0 136 maximum: 2 137 138 termination-gpios: true 139 termination-ohms: true 140 141required: 142 - compatible 143 - reg 144 - interrupts 145 146allOf: 147 - $ref: can-controller.yaml# 148 - if: 149 properties: 150 compatible: 151 contains: 152 const: nxp,s32g2-flexcan 153 then: 154 properties: 155 interrupts: 156 items: 157 - description: Message Buffer interrupt for mailboxes 0-7 and Enhanced RX FIFO 158 - description: Device state change 159 - description: Bus Error detection 160 - description: Message Buffer interrupt for mailboxes 8-127 161 interrupt-names: 162 items: 163 - const: mb-0 164 - const: state 165 - const: berr 166 - const: mb-1 167 required: 168 - interrupt-names 169 else: 170 properties: 171 interrupts: 172 maxItems: 1 173 interrupt-names: false 174 175additionalProperties: false 176 177examples: 178 - | 179 can@1c000 { 180 compatible = "fsl,p1010-flexcan"; 181 reg = <0x1c000 0x1000>; 182 interrupts = <48 0x2>; 183 interrupt-parent = <&mpic>; 184 clock-frequency = <200000000>; 185 fsl,clk-source = /bits/ 8 <0>; 186 }; 187 - | 188 #include <dt-bindings/interrupt-controller/irq.h> 189 190 can@2090000 { 191 compatible = "fsl,imx6q-flexcan"; 192 reg = <0x02090000 0x4000>; 193 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&clks 1>, <&clks 2>; 195 clock-names = "ipg", "per"; 196 fsl,stop-mode = <&gpr 0x34 28>; 197 fsl,scu-index = /bits/ 8 <1>; 198 }; 199 - | 200 #include <dt-bindings/interrupt-controller/irq.h> 201 #include <dt-bindings/gpio/gpio.h> 202 203 can@2090000 { 204 compatible = "fsl,imx6q-flexcan"; 205 reg = <0x02090000 0x4000>; 206 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clks 1>, <&clks 2>; 208 clock-names = "ipg", "per"; 209 fsl,stop-mode = <&gpr 0x34 28>; 210 termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 211 termination-ohms = <120>; 212 }; 213