1*7675a1dcSFlorian Fainelli# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*7675a1dcSFlorian Fainelli%YAML 1.2 3*7675a1dcSFlorian Fainelli--- 4*7675a1dcSFlorian Fainelli$id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml# 5*7675a1dcSFlorian Fainelli$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7675a1dcSFlorian Fainelli 7*7675a1dcSFlorian Fainellititle: MDIO bus multiplexer found in Broadcom iProc based SoCs. 8*7675a1dcSFlorian Fainelli 9*7675a1dcSFlorian Fainellimaintainers: 10*7675a1dcSFlorian Fainelli - Florian Fainelli <f.fainelli@gmail.com> 11*7675a1dcSFlorian Fainelli 12*7675a1dcSFlorian Fainellidescription: 13*7675a1dcSFlorian Fainelli This MDIO bus multiplexer defines buses that could be internal as well as 14*7675a1dcSFlorian Fainelli external to SoCs and could accept MDIO transaction compatible to C-22 or 15*7675a1dcSFlorian Fainelli C-45 Clause. When child bus is selected, one needs to select these two 16*7675a1dcSFlorian Fainelli properties as well to generate desired MDIO transaction on appropriate bus. 17*7675a1dcSFlorian Fainelli 18*7675a1dcSFlorian FainelliallOf: 19*7675a1dcSFlorian Fainelli - $ref: /schemas/net/mdio-mux.yaml# 20*7675a1dcSFlorian Fainelli 21*7675a1dcSFlorian Fainelliproperties: 22*7675a1dcSFlorian Fainelli compatible: 23*7675a1dcSFlorian Fainelli const: brcm,mdio-mux-iproc 24*7675a1dcSFlorian Fainelli 25*7675a1dcSFlorian Fainelli reg: 26*7675a1dcSFlorian Fainelli maxItems: 1 27*7675a1dcSFlorian Fainelli 28*7675a1dcSFlorian Fainelli clocks: 29*7675a1dcSFlorian Fainelli maxItems: 1 30*7675a1dcSFlorian Fainelli description: core clock driving the MDIO block 31*7675a1dcSFlorian Fainelli 32*7675a1dcSFlorian Fainelli 33*7675a1dcSFlorian Fainellirequired: 34*7675a1dcSFlorian Fainelli - compatible 35*7675a1dcSFlorian Fainelli - reg 36*7675a1dcSFlorian Fainelli 37*7675a1dcSFlorian FainelliunevaluatedProperties: false 38*7675a1dcSFlorian Fainelli 39*7675a1dcSFlorian Fainelliexamples: 40*7675a1dcSFlorian Fainelli - | 41*7675a1dcSFlorian Fainelli mdio_mux_iproc: mdio-mux@66020000 { 42*7675a1dcSFlorian Fainelli compatible = "brcm,mdio-mux-iproc"; 43*7675a1dcSFlorian Fainelli reg = <0x66020000 0x250>; 44*7675a1dcSFlorian Fainelli #address-cells = <1>; 45*7675a1dcSFlorian Fainelli #size-cells = <0>; 46*7675a1dcSFlorian Fainelli 47*7675a1dcSFlorian Fainelli mdio@0 { 48*7675a1dcSFlorian Fainelli reg = <0x0>; 49*7675a1dcSFlorian Fainelli #address-cells = <1>; 50*7675a1dcSFlorian Fainelli #size-cells = <0>; 51*7675a1dcSFlorian Fainelli 52*7675a1dcSFlorian Fainelli pci_phy0: pci-phy@0 { 53*7675a1dcSFlorian Fainelli compatible = "brcm,ns2-pcie-phy"; 54*7675a1dcSFlorian Fainelli reg = <0x0>; 55*7675a1dcSFlorian Fainelli #phy-cells = <0>; 56*7675a1dcSFlorian Fainelli }; 57*7675a1dcSFlorian Fainelli }; 58*7675a1dcSFlorian Fainelli 59*7675a1dcSFlorian Fainelli mdio@7 { 60*7675a1dcSFlorian Fainelli reg = <0x7>; 61*7675a1dcSFlorian Fainelli #address-cells = <1>; 62*7675a1dcSFlorian Fainelli #size-cells = <0>; 63*7675a1dcSFlorian Fainelli 64*7675a1dcSFlorian Fainelli pci_phy1: pci-phy@0 { 65*7675a1dcSFlorian Fainelli compatible = "brcm,ns2-pcie-phy"; 66*7675a1dcSFlorian Fainelli reg = <0x0>; 67*7675a1dcSFlorian Fainelli #phy-cells = <0>; 68*7675a1dcSFlorian Fainelli }; 69*7675a1dcSFlorian Fainelli }; 70*7675a1dcSFlorian Fainelli 71*7675a1dcSFlorian Fainelli mdio@10 { 72*7675a1dcSFlorian Fainelli reg = <0x10>; 73*7675a1dcSFlorian Fainelli #address-cells = <1>; 74*7675a1dcSFlorian Fainelli #size-cells = <0>; 75*7675a1dcSFlorian Fainelli 76*7675a1dcSFlorian Fainelli gphy0: eth-phy@10 { 77*7675a1dcSFlorian Fainelli reg = <0x10>; 78*7675a1dcSFlorian Fainelli }; 79*7675a1dcSFlorian Fainelli }; 80*7675a1dcSFlorian Fainelli }; 81