1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright 2019 BayLibre, SAS 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Amlogic Meson DWMAC Ethernet controller 9 10maintainers: 11 - Neil Armstrong <narmstrong@baylibre.com> 12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 13 14# We need a select here so we don't match all nodes with 'snps,dwmac' 15select: 16 properties: 17 compatible: 18 contains: 19 enum: 20 - amlogic,meson6-dwmac 21 - amlogic,meson8b-dwmac 22 - amlogic,meson8m2-dwmac 23 - amlogic,meson-gxbb-dwmac 24 - amlogic,meson-axg-dwmac 25 - amlogic,meson-g12a-dwmac 26 required: 27 - compatible 28 29allOf: 30 - $ref: "snps,dwmac.yaml#" 31 - if: 32 properties: 33 compatible: 34 contains: 35 enum: 36 - amlogic,meson8b-dwmac 37 - amlogic,meson8m2-dwmac 38 - amlogic,meson-gxbb-dwmac 39 - amlogic,meson-axg-dwmac 40 - amlogic,meson-g12a-dwmac 41 42 then: 43 properties: 44 clocks: 45 minItems: 3 46 maxItems: 4 47 items: 48 - description: GMAC main clock 49 - description: First parent clock of the internal mux 50 - description: Second parent clock of the internal mux 51 - description: The clock which drives the timing adjustment logic 52 53 clock-names: 54 minItems: 3 55 maxItems: 4 56 items: 57 - const: stmmaceth 58 - const: clkin0 59 - const: clkin1 60 - const: timing-adjustment 61 62 amlogic,tx-delay-ns: 63 $ref: /schemas/types.yaml#/definitions/uint32 64 description: 65 The internal RGMII TX clock delay (provided by this driver) in 66 nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns. 67 When phy-mode is set to "rgmii" then the TX delay should be 68 explicitly configured. When not configured a fallback of 2ns is 69 used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid" 70 the TX clock delay is already provided by the PHY. In that case 71 this property should be set to 0ns (which disables the TX clock 72 delay in the MAC to prevent the clock from going off because both 73 PHY and MAC are adding a delay). 74 Any configuration is ignored when the phy-mode is set to "rmii". 75 76 amlogic,rx-delay-ns: 77 deprecated: true 78 enum: 79 - 0 80 - 2 81 default: 0 82 description: 83 The internal RGMII RX clock delay in nanoseconds. Deprecated, use 84 rx-internal-delay-ps instead. 85 86 rx-internal-delay-ps: 87 default: 0 88 89 - if: 90 properties: 91 compatible: 92 contains: 93 enum: 94 - amlogic,meson8b-dwmac 95 - amlogic,meson8m2-dwmac 96 - amlogic,meson-gxbb-dwmac 97 - amlogic,meson-axg-dwmac 98 then: 99 properties: 100 rx-internal-delay-ps: 101 enum: 102 - 0 103 - 2000 104 105 - if: 106 properties: 107 compatible: 108 contains: 109 enum: 110 - amlogic,meson-g12a-dwmac 111 then: 112 properties: 113 rx-internal-delay-ps: 114 enum: 115 - 0 116 - 200 117 - 400 118 - 600 119 - 800 120 - 1000 121 - 1200 122 - 1400 123 - 1600 124 - 1800 125 - 2000 126 - 2200 127 - 2400 128 - 2600 129 - 2800 130 - 3000 131 132properties: 133 compatible: 134 additionalItems: true 135 maxItems: 3 136 items: 137 - enum: 138 - amlogic,meson6-dwmac 139 - amlogic,meson8b-dwmac 140 - amlogic,meson8m2-dwmac 141 - amlogic,meson-gxbb-dwmac 142 - amlogic,meson-axg-dwmac 143 - amlogic,meson-g12a-dwmac 144 contains: 145 enum: 146 - snps,dwmac-3.70a 147 - snps,dwmac 148 149 reg: 150 items: 151 - description: 152 The first register range should be the one of the DWMAC controller 153 - description: 154 The second range is is for the Amlogic specific configuration 155 (for example the PRG_ETHERNET register range on Meson8b and newer) 156 157required: 158 - compatible 159 - reg 160 - interrupts 161 - interrupt-names 162 - clocks 163 - clock-names 164 - phy-mode 165 166unevaluatedProperties: false 167 168examples: 169 - | 170 ethmac: ethernet@c9410000 { 171 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 172 reg = <0xc9410000 0x10000>, <0xc8834540 0x8>; 173 interrupts = <8>; 174 interrupt-names = "macirq"; 175 clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>; 176 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; 177 phy-mode = "rgmii"; 178 }; 179