1* AMD 10GbE driver (amd-xgbe) 2 3Required properties: 4- compatible: Should be "amd,xgbe-seattle-v1a" 5- reg: Address and length of the register sets for the device 6 - MAC registers 7 - PCS registers 8 - SerDes Rx/Tx registers 9 - SerDes integration registers (1/2) 10 - SerDes integration registers (2/2) 11- interrupt-parent: Should be the phandle for the interrupt controller 12 that services interrupts for this device 13- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt 14 listed is required and is the general device interrupt. If the optional 15 amd,per-channel-interrupt property is specified, then one additional 16 interrupt for each DMA channel supported by the device should be specified. 17 The last interrupt listed should be the PCS auto-negotiation interrupt. 18- clocks: 19 - DMA clock for the amd-xgbe device (used for calculating the 20 correct Rx interrupt watchdog timer value on a DMA channel 21 for coalescing) 22 - PTP clock for the amd-xgbe device 23- clock-names: Should be the names of the clocks 24 - "dma_clk" for the DMA clock 25 - "ptp_clk" for the PTP clock 26- phy-mode: See ethernet.txt file in the same directory 27 28Optional properties: 29- mac-address: mac address to be assigned to the device. Can be overridden 30 by UEFI. 31- dma-coherent: Present if dma operations are coherent 32- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate 33 a unique interrupt for each DMA channel - this requires an additional 34 interrupt be configured for each DMA channel 35- amd,speed-set: Speed capabilities of the device 36 0 - 1GbE and 10GbE (default) 37 1 - 2.5GbE and 10GbE 38 39The following optional properties are represented by an array with each 40value corresponding to a particular speed. The first array value represents 41the setting for the 1GbE speed, the second value for the 2.5GbE speed and 42the third value for the 10GbE speed. All three values are required if the 43property is used. 44- amd,serdes-blwc: Baseline wandering correction enablement 45 0 - Off 46 1 - On 47- amd,serdes-cdr-rate: CDR rate speed selection 48- amd,serdes-pq-skew: PQ (data sampling) skew 49- amd,serdes-tx-amp: TX amplitude boost 50- amd,serdes-dfe-tap-config: DFE taps available to run 51- amd,serdes-dfe-tap-enable: DFE taps to enable 52 53Example: 54 xgbe@e0700000 { 55 compatible = "amd,xgbe-seattle-v1a"; 56 reg = <0 0xe0700000 0 0x80000>, 57 <0 0xe0780000 0 0x80000>, 58 <0 0xe1240800 0 0x00400>, 59 <0 0xe1250000 0 0x00060>, 60 <0 0xe1250080 0 0x00004>; 61 interrupt-parent = <&gic>; 62 interrupts = <0 325 4>, 63 <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, 64 <0 323 4>; 65 amd,per-channel-interrupt; 66 clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; 67 clock-names = "dma_clk", "ptp_clk"; 68 phy-mode = "xgmii"; 69 mac-address = [ 02 a1 a2 a3 a4 a5 ]; 70 amd,speed-set = <0>; 71 amd,serdes-blwc = <1>, <1>, <0>; 72 amd,serdes-cdr-rate = <2>, <2>, <7>; 73 amd,serdes-pq-skew = <10>, <10>, <30>; 74 amd,serdes-tx-amp = <15>, <15>, <10>; 75 amd,serdes-dfe-tap-config = <3>, <3>, <1>; 76 amd,serdes-dfe-tap-enable = <0>, <0>, <127>; 77 }; 78