xref: /linux/Documentation/devicetree/bindings/net/actions,owl-emac.yaml (revision 172cdcaefea5c297fdb3d20b7d5aff60ae4fbce6) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/actions,owl-emac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Actions Semi Owl SoCs Ethernet MAC Controller
8
9maintainers:
10  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
11
12description: |
13  This Ethernet MAC is used on the Owl family of SoCs from Actions Semi.
14  It provides the RMII and SMII interfaces and is compliant with the
15  IEEE 802.3 CSMA/CD standard, supporting both half-duplex and full-duplex
16  operation modes at 10/100 Mb/s data transfer rates.
17
18allOf:
19  - $ref: "ethernet-controller.yaml#"
20
21properties:
22  compatible:
23    oneOf:
24      - const: actions,owl-emac
25      - items:
26          - enum:
27              - actions,s500-emac
28          - const: actions,owl-emac
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    minItems: 2
38    maxItems: 2
39
40  clock-names:
41    additionalItems: false
42    items:
43      - const: eth
44      - const: rmii
45
46  resets:
47    maxItems: 1
48
49  actions,ethcfg:
50    $ref: /schemas/types.yaml#/definitions/phandle
51    description:
52      Phandle to the device containing custom config.
53
54required:
55  - compatible
56  - reg
57  - interrupts
58  - clocks
59  - clock-names
60  - resets
61  - phy-mode
62  - phy-handle
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/actions,s500-cmu.h>
69    #include <dt-bindings/interrupt-controller/arm-gic.h>
70    #include <dt-bindings/reset/actions,s500-reset.h>
71
72    ethernet@b0310000 {
73        compatible = "actions,s500-emac", "actions,owl-emac";
74        reg = <0xb0310000 0x10000>;
75        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
76        clocks = <&cmu 59 /*CLK_ETHERNET*/>, <&cmu CLK_RMII_REF>;
77        clock-names = "eth", "rmii";
78        resets = <&cmu RESET_ETHERNET>;
79        phy-mode = "rmii";
80        phy-handle = <&eth_phy>;
81
82        mdio {
83            #address-cells = <1>;
84            #size-cells = <0>;
85
86            eth_phy: ethernet-phy@3 {
87                reg = <0x3>;
88                interrupt-parent = <&sirq>;
89                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
90            };
91        };
92    };
93