xref: /linux/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml (revision ff124bbbca1d3a07fa1392ffdbbdeece71f68ece) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI DaVinci NAND controller
8
9maintainers:
10  - Marcus Folkesson <marcus.folkesson@gmail.com>
11
12allOf:
13  - $ref: nand-controller.yaml
14
15properties:
16  compatible:
17    enum:
18      - ti,davinci-nand
19      - ti,keystone-nand
20
21  reg:
22    items:
23      - description: Access window.
24      - description: AEMIF control registers.
25
26  partitions:
27    type: object
28    required:
29      - compatible
30
31  ti,davinci-chipselect:
32    description:
33      Number of chipselect. Indicate on the davinci_nand driver which
34      chipselect is used for accessing the nand.
35    $ref: /schemas/types.yaml#/definitions/uint32
36    enum: [0, 1, 2, 3]
37
38  ti,davinci-mask-ale:
39    description:
40      Mask for ALE. Needed for executing address phase. These offset will be
41      added to the base address for the chip select space the NAND Flash
42      device is connected to.
43    $ref: /schemas/types.yaml#/definitions/uint32
44    default: 0x08
45
46  ti,davinci-mask-cle:
47    description:
48      Mask for CLE. Needed for executing command phase. These offset will be
49      added to the base address for the chip select space the NAND Flash device
50      is connected to.
51    $ref: /schemas/types.yaml#/definitions/uint32
52    default: 0x10
53
54  ti,davinci-mask-chipsel:
55    description:
56      Mask for chipselect address. Needed to mask addresses for given
57      chipselect.
58    $ref: /schemas/types.yaml#/definitions/uint32
59    default: 0
60
61  ti,davinci-ecc-bits:
62    description: Used ECC bits.
63    enum: [1, 4]
64
65  ti,davinci-ecc-mode:
66    description: Operation mode of the NAND ECC mode.
67    $ref: /schemas/types.yaml#/definitions/string
68    enum: [none, soft, hw, on-die]
69    deprecated: true
70
71  ti,davinci-nand-buswidth:
72    description: Bus width to the NAND chip.
73    $ref: /schemas/types.yaml#/definitions/uint32
74    enum: [8, 16]
75    default: 8
76    deprecated: true
77
78  ti,davinci-nand-use-bbt:
79    type: boolean
80    description:
81      Use flash based bad block table support. OOB identifier is saved in OOB
82      area.
83    deprecated: true
84
85required:
86  - compatible
87  - reg
88  - ti,davinci-chipselect
89
90unevaluatedProperties: false
91
92examples:
93  - |
94    bus {
95      #address-cells = <2>;
96      #size-cells = <1>;
97
98      nand-controller@2000000,0 {
99        compatible = "ti,davinci-nand";
100        #address-cells = <1>;
101        #size-cells = <0>;
102        reg = <0 0x02000000 0x02000000>,
103              <1 0x00000000 0x00008000>;
104
105        ti,davinci-chipselect = <1>;
106        ti,davinci-mask-ale = <0>;
107        ti,davinci-mask-cle = <0>;
108        ti,davinci-mask-chipsel = <0>;
109
110        ti,davinci-nand-buswidth = <16>;
111        ti,davinci-ecc-mode = "hw";
112        ti,davinci-ecc-bits = <4>;
113        ti,davinci-nand-use-bbt;
114
115        partitions {
116          compatible = "fixed-partitions";
117          #address-cells = <1>;
118          #size-cells = <1>;
119
120          partition@0 {
121            label = "u-boot env";
122            reg = <0 0x020000>;
123          };
124        };
125      };
126    };
127