1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm NAND controller 8 9maintainers: 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,sdx75-nand 18 - const: qcom,sdx55-nand 19 - items: 20 - enum: 21 - qcom,ipq806x-nand 22 - qcom,ipq4019-nand 23 - qcom,ipq6018-nand 24 - qcom,ipq8074-nand 25 - qcom,mdm9607-nand 26 - qcom,sdx55-nand 27 28 reg: 29 maxItems: 1 30 31 clocks: 32 minItems: 1 33 items: 34 - description: Core Clock 35 - description: Always ON Clock 36 37 clock-names: 38 minItems: 1 39 items: 40 - const: core 41 - const: aon 42 43 qcom,cmd-crci: 44 $ref: /schemas/types.yaml#/definitions/uint32 45 description: 46 Must contain the ADM command type CRCI block instance number specified for 47 the NAND controller on the given platform 48 49 qcom,data-crci: 50 $ref: /schemas/types.yaml#/definitions/uint32 51 description: 52 Must contain the ADM data type CRCI block instance number specified for 53 the NAND controller on the given platform 54 55patternProperties: 56 "^nand@[a-f0-9]$": 57 type: object 58 $ref: raw-nand-chip.yaml 59 properties: 60 61 nand-bus-width: 62 const: 8 63 64 nand-ecc-strength: 65 enum: [1, 4, 8] 66 67 nand-ecc-step-size: 68 enum: 69 - 512 70 71 qcom,boot-partitions: 72 $ref: /schemas/types.yaml#/definitions/uint32-matrix 73 items: 74 items: 75 - description: offset 76 - description: size 77 description: 78 Boot partition use a different layout where the 4 bytes of spare 79 data are not protected by ECC. Use this to declare these special 80 partitions by defining first the offset and then the size. 81 82 It's in the form of <offset1 size1 offset2 size2 offset3 ...> 83 and should be declared in ascending order. 84 85 Refer to the ipq8064 example on how to use this special binding. 86 87 unevaluatedProperties: false 88 89allOf: 90 - $ref: nand-controller.yaml# 91 92 - if: 93 properties: 94 compatible: 95 contains: 96 const: qcom,ipq806x-nand 97 then: 98 properties: 99 dmas: 100 items: 101 - description: rxtx DMA channel 102 103 dma-names: 104 items: 105 - const: rxtx 106 107 # On MDM9607, the OS can only control a single clock. 108 # The 3 hardware clocks (core, aon, ahb) are invisible to the OS. 109 - if: 110 properties: 111 compatible: 112 contains: 113 enum: 114 - qcom,mdm9607-nand 115 then: 116 properties: 117 clocks: 118 maxItems: 1 119 clock-names: 120 maxItems: 1 121 else: 122 properties: 123 clocks: 124 minItems: 2 125 clock-names: 126 minItems: 2 127 128 - if: 129 properties: 130 compatible: 131 contains: 132 enum: 133 - qcom,sdx75-nand 134 135 then: 136 properties: 137 iommus: 138 maxItems: 1 139 140 - if: 141 properties: 142 compatible: 143 contains: 144 enum: 145 - qcom,ipq4019-nand 146 - qcom,ipq6018-nand 147 - qcom,ipq8074-nand 148 - qcom,mdm9607-nand 149 - qcom,sdx55-nand 150 151 then: 152 properties: 153 dmas: 154 items: 155 - description: tx DMA channel 156 - description: rx DMA channel 157 - description: cmd DMA channel 158 159 dma-names: 160 items: 161 - const: tx 162 - const: rx 163 - const: cmd 164 165 qcom,cmd-crci: false 166 qcom,data-crci: false 167 168 patternProperties: 169 "^nand@[a-f0-9]$": 170 properties: 171 qcom,boot-partitions: false 172 173required: 174 - compatible 175 - reg 176 - clocks 177 - clock-names 178 179unevaluatedProperties: false 180 181examples: 182 - | 183 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 184 nand-controller@1ac00000 { 185 compatible = "qcom,ipq806x-nand"; 186 reg = <0x1ac00000 0x800>; 187 188 clocks = <&gcc EBI2_CLK>, 189 <&gcc EBI2_AON_CLK>; 190 clock-names = "core", "aon"; 191 192 dmas = <&adm_dma 3>; 193 dma-names = "rxtx"; 194 qcom,cmd-crci = <15>; 195 qcom,data-crci = <3>; 196 197 #address-cells = <1>; 198 #size-cells = <0>; 199 200 nand@0 { 201 reg = <0>; 202 203 nand-ecc-strength = <4>; 204 nand-bus-width = <8>; 205 206 qcom,boot-partitions = <0x0 0x58a0000>; 207 208 partitions { 209 compatible = "fixed-partitions"; 210 #address-cells = <1>; 211 #size-cells = <1>; 212 213 partition@0 { 214 label = "boot-nand"; 215 reg = <0 0x58a0000>; 216 }; 217 218 partition@58a0000 { 219 label = "fs-nand"; 220 reg = <0x58a0000 0x4000000>; 221 }; 222 }; 223 }; 224 }; 225 226 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 227 nand-controller@79b0000 { 228 compatible = "qcom,ipq4019-nand"; 229 reg = <0x79b0000 0x1000>; 230 231 clocks = <&gcc GCC_QPIC_CLK>, 232 <&gcc GCC_QPIC_AHB_CLK>; 233 clock-names = "core", "aon"; 234 235 dmas = <&qpicbam 0>, 236 <&qpicbam 1>, 237 <&qpicbam 2>; 238 dma-names = "tx", "rx", "cmd"; 239 240 #address-cells = <1>; 241 #size-cells = <0>; 242 243 nand@0 { 244 reg = <0>; 245 nand-ecc-strength = <4>; 246 nand-bus-width = <8>; 247 248 partitions { 249 compatible = "fixed-partitions"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 253 partition@0 { 254 label = "boot-nand"; 255 reg = <0 0x58a0000>; 256 }; 257 258 partition@58a0000 { 259 label = "fs-nand"; 260 reg = <0x58a0000 0x4000000>; 261 }; 262 }; 263 }; 264 }; 265 266... 267