xref: /linux/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml (revision e598511b0bfe7d9fd5165d53f1afb94e1a9be62d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm NAND controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    enum:
15      - qcom,ipq806x-nand
16      - qcom,ipq4019-nand
17      - qcom,ipq6018-nand
18      - qcom,ipq8074-nand
19      - qcom,sdx55-nand
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: Core Clock
27      - description: Always ON Clock
28
29  clock-names:
30    items:
31      - const: core
32      - const: aon
33
34patternProperties:
35  "^nand@[a-f0-9]$":
36    type: object
37    properties:
38      nand-bus-width:
39        const: 8
40
41      nand-ecc-strength:
42        enum: [1, 4, 8]
43
44      nand-ecc-step-size:
45        enum:
46          - 512
47
48allOf:
49  - $ref: "nand-controller.yaml#"
50
51  - if:
52      properties:
53        compatible:
54          contains:
55            const: qcom,ipq806x-nand
56    then:
57      properties:
58        dmas:
59          items:
60            - description: rxtx DMA channel
61
62        dma-names:
63          items:
64            - const: rxtx
65
66        qcom,cmd-crci:
67          $ref: /schemas/types.yaml#/definitions/uint32
68          description:
69            Must contain the ADM command type CRCI block instance number
70            specified for the NAND controller on the given platform
71
72        qcom,data-crci:
73          $ref: /schemas/types.yaml#/definitions/uint32
74          description:
75            Must contain the ADM data type CRCI block instance number
76            specified for the NAND controller on the given platform
77
78  - if:
79      properties:
80        compatible:
81          contains:
82            enum:
83              - qcom,ipq4019-nand
84              - qcom,ipq6018-nand
85              - qcom,ipq8074-nand
86              - qcom,sdx55-nand
87
88    then:
89      properties:
90        dmas:
91          items:
92            - description: tx DMA channel
93            - description: rx DMA channel
94            - description: cmd DMA channel
95
96        dma-names:
97          items:
98            - const: tx
99            - const: rx
100            - const: cmd
101
102  - if:
103      properties:
104        compatible:
105          contains:
106            enum:
107              - qcom,ipq806x-nand
108
109    then:
110      properties:
111        qcom,boot-partitions:
112          $ref: /schemas/types.yaml#/definitions/uint32-matrix
113          items:
114            items:
115              - description: offset
116              - description: size
117          description:
118            Boot partition use a different layout where the 4 bytes of spare
119            data are not protected by ECC. Use this to declare these special
120            partitions by defining first the offset and then the size.
121
122            It's in the form of <offset1 size1 offset2 size2 offset3 ...>
123            and should be declared in ascending order.
124
125            Refer to the ipq8064 example on how to use this special binding.
126
127required:
128  - compatible
129  - reg
130  - clocks
131  - clock-names
132
133unevaluatedProperties: false
134
135examples:
136  - |
137    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
138    nand-controller@1ac00000 {
139      compatible = "qcom,ipq806x-nand";
140      reg = <0x1ac00000 0x800>;
141
142      clocks = <&gcc EBI2_CLK>,
143               <&gcc EBI2_AON_CLK>;
144      clock-names = "core", "aon";
145
146      dmas = <&adm_dma 3>;
147      dma-names = "rxtx";
148      qcom,cmd-crci = <15>;
149      qcom,data-crci = <3>;
150
151      #address-cells = <1>;
152      #size-cells = <0>;
153
154      nand@0 {
155        reg = <0>;
156
157        nand-ecc-strength = <4>;
158        nand-bus-width = <8>;
159
160        qcom,boot-partitions = <0x0 0x58a0000>;
161
162        partitions {
163          compatible = "fixed-partitions";
164          #address-cells = <1>;
165          #size-cells = <1>;
166
167          partition@0 {
168            label = "boot-nand";
169            reg = <0 0x58a0000>;
170          };
171
172          partition@58a0000 {
173            label = "fs-nand";
174            reg = <0x58a0000 0x4000000>;
175          };
176        };
177      };
178    };
179
180    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
181    nand-controller@79b0000 {
182      compatible = "qcom,ipq4019-nand";
183      reg = <0x79b0000 0x1000>;
184
185      clocks = <&gcc GCC_QPIC_CLK>,
186               <&gcc GCC_QPIC_AHB_CLK>;
187      clock-names = "core", "aon";
188
189      dmas = <&qpicbam 0>,
190             <&qpicbam 1>,
191             <&qpicbam 2>;
192      dma-names = "tx", "rx", "cmd";
193
194      #address-cells = <1>;
195      #size-cells = <0>;
196
197      nand@0 {
198        reg = <0>;
199        nand-ecc-strength = <4>;
200        nand-bus-width = <8>;
201
202        partitions {
203          compatible = "fixed-partitions";
204          #address-cells = <1>;
205          #size-cells = <1>;
206
207          partition@0 {
208            label = "boot-nand";
209            reg = <0 0x58a0000>;
210          };
211
212          partition@58a0000 {
213            label = "fs-nand";
214            reg = <0x58a0000 0x4000000>;
215          };
216        };
217      };
218    };
219
220...
221