xref: /linux/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml (revision 411a1215a07904cafbea683f4b2908f1310946a1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm NAND controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    enum:
15      - qcom,ipq806x-nand
16      - qcom,ipq4019-nand
17      - qcom,ipq6018-nand
18      - qcom,ipq8074-nand
19      - qcom,sdx55-nand
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: Core Clock
27      - description: Always ON Clock
28
29  clock-names:
30    items:
31      - const: core
32      - const: aon
33
34patternProperties:
35  "^nand@[a-f0-9]$":
36    type: object
37    properties:
38      nand-bus-width:
39        const: 8
40
41      nand-ecc-strength:
42        enum: [1, 4, 8]
43
44      nand-ecc-step-size:
45        enum:
46          - 512
47
48      qcom,boot-partitions:
49        $ref: /schemas/types.yaml#/definitions/uint32-matrix
50        items:
51          items:
52            - description: offset
53            - description: size
54        description:
55          Boot partition use a different layout where the 4 bytes of spare
56          data are not protected by ECC. Use this to declare these special
57          partitions by defining first the offset and then the size.
58
59          It's in the form of <offset1 size1 offset2 size2 offset3 ...>
60          and should be declared in ascending order.
61
62          Refer to the ipq8064 example on how to use this special binding.
63
64allOf:
65  - $ref: nand-controller.yaml#
66
67  - if:
68      properties:
69        compatible:
70          contains:
71            const: qcom,ipq806x-nand
72    then:
73      properties:
74        dmas:
75          items:
76            - description: rxtx DMA channel
77
78        dma-names:
79          items:
80            - const: rxtx
81
82        qcom,cmd-crci:
83          $ref: /schemas/types.yaml#/definitions/uint32
84          description:
85            Must contain the ADM command type CRCI block instance number
86            specified for the NAND controller on the given platform
87
88        qcom,data-crci:
89          $ref: /schemas/types.yaml#/definitions/uint32
90          description:
91            Must contain the ADM data type CRCI block instance number
92            specified for the NAND controller on the given platform
93
94  - if:
95      properties:
96        compatible:
97          contains:
98            enum:
99              - qcom,ipq4019-nand
100              - qcom,ipq6018-nand
101              - qcom,ipq8074-nand
102              - qcom,sdx55-nand
103
104    then:
105      properties:
106        dmas:
107          items:
108            - description: tx DMA channel
109            - description: rx DMA channel
110            - description: cmd DMA channel
111
112        dma-names:
113          items:
114            - const: tx
115            - const: rx
116            - const: cmd
117
118  - if:
119      properties:
120        compatible:
121          contains:
122            enum:
123              - qcom,ipq806x-nand
124
125    then:
126      patternProperties:
127        "^nand@[a-f0-9]$":
128          properties:
129            qcom,boot-partitions: true
130    else:
131      patternProperties:
132        "^nand@[a-f0-9]$":
133          properties:
134            qcom,boot-partitions: false
135
136required:
137  - compatible
138  - reg
139  - clocks
140  - clock-names
141
142unevaluatedProperties: false
143
144examples:
145  - |
146    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
147    nand-controller@1ac00000 {
148        compatible = "qcom,ipq806x-nand";
149        reg = <0x1ac00000 0x800>;
150
151        clocks = <&gcc EBI2_CLK>,
152                 <&gcc EBI2_AON_CLK>;
153        clock-names = "core", "aon";
154
155        dmas = <&adm_dma 3>;
156        dma-names = "rxtx";
157        qcom,cmd-crci = <15>;
158        qcom,data-crci = <3>;
159
160        #address-cells = <1>;
161        #size-cells = <0>;
162
163        nand@0 {
164            reg = <0>;
165
166            nand-ecc-strength = <4>;
167            nand-bus-width = <8>;
168
169            qcom,boot-partitions = <0x0 0x58a0000>;
170
171            partitions {
172                compatible = "fixed-partitions";
173                #address-cells = <1>;
174                #size-cells = <1>;
175
176                partition@0 {
177                    label = "boot-nand";
178                    reg = <0 0x58a0000>;
179                };
180
181                partition@58a0000 {
182                    label = "fs-nand";
183                    reg = <0x58a0000 0x4000000>;
184                };
185            };
186        };
187    };
188
189    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
190    nand-controller@79b0000 {
191        compatible = "qcom,ipq4019-nand";
192        reg = <0x79b0000 0x1000>;
193
194        clocks = <&gcc GCC_QPIC_CLK>,
195                 <&gcc GCC_QPIC_AHB_CLK>;
196        clock-names = "core", "aon";
197
198        dmas = <&qpicbam 0>,
199               <&qpicbam 1>,
200               <&qpicbam 2>;
201        dma-names = "tx", "rx", "cmd";
202
203        #address-cells = <1>;
204        #size-cells = <0>;
205
206        nand@0 {
207            reg = <0>;
208            nand-ecc-strength = <4>;
209            nand-bus-width = <8>;
210
211            partitions {
212                compatible = "fixed-partitions";
213                #address-cells = <1>;
214                #size-cells = <1>;
215
216                partition@0 {
217                    label = "boot-nand";
218                    reg = <0 0x58a0000>;
219                };
220
221                partition@58a0000 {
222                    label = "fs-nand";
223                    reg = <0x58a0000 0x4000000>;
224                };
225            };
226        };
227    };
228
229...
230